Baud Rate Generator for UART (VHDL)

Overview

This project implements a simple Baud Rate Generator in VHDL for FPGA-based UART communication. The generator produces a periodic tick signal at 153,600 Hz (16x oversampling for a 9,600 baud rate) from a 50 MHz input clock. This is targeted for Spartan 3E FPGA.

Key Parameters:

• Input Clock: 50 MHz
• Target Baud Rate: 9,600
• Oversampling Factor: 16x
• Tick Frequency: 9,600 × 16 = 153,600 Hz
• Counter Divisor: ⌈50,000,000 / 153,600⌉ ≈ 326 (rounded for accuracy)

Design File: design.vhd

Architecture: Behavioral

• Counter: 9-bit unsigned counter (count) initialized to 0.
• Logic (synchronous on rising edge of clk):
  • If count == 325 (divisor -1), reset count to 0 and assert tick = '1'.
  • Else, increment count and deassert tick = '0'.
• This generates a single-cycle tick pulse every 326 clock cycles.

Accuracy Note: Using 326 gives ~153,374 Hz (0.15% error), suitable for UART.

Testbench File: testbench.vhd

Purpose

Verifies the BaudRate_Generator functionality through simulation.

Key Components

• UUT Instantiation: Maps clk and tick.
• Clock Generator: Symmetric 100 MHz clock (10 ns period) for simulation.
• Stimulus: Minimal - waits 100 ns to observe initial ticks.

How to Simulate

1. Compile design.vhd and testbench.vhd in a VHDL simulator (e.g., Xilinx Vivado).
2. Run the simulation for at least 1 ms to observe multiple ticks.
3. Use waveform viewer to check tick signal timing.

Expected Behavior

• tick pulses high every ~3.26 µs (326 × 50 ns at real clk; adjust for sim clk).
• Verify frequency, no glitches.

Synthesis & Implementation

• Target: Xilinx Spartan 3E FPGA (50 MHz clk).
• Use Xilinx ISE/Vivado for synthesis.
• Resource Usage: Minimal (small counter).

Improvements

• Parameterize divisor/baud rate/clk freq using generics.
• Add reset input.
• Enhance testbench: Assertions for tick period, frequency measurement, edge cases.
• Half-period tick for UART center sampling.

References

• UART oversampling: 16x standard for reliable bit sampling.
• Divisor calc: clk_freq / (baud × oversample)