Add Zhaoxin support for RDRAND/RDSEED/ADX/SHA/AVX2 feature#1316
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AlanSong-OC-ZX wants to merge 2 commits intoweidai11:masterfrom
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Add Zhaoxin support for RDRAND/RDSEED/ADX/SHA/AVX2 feature#1316AlanSong-OC-ZX wants to merge 2 commits intoweidai11:masterfrom
AlanSong-OC-ZX wants to merge 2 commits intoweidai11:masterfrom
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According to public documentation, starting with VIA's Samuel 2 architecture, the cache line size can be obtained by using the CPUID instruction with leaf 0x80000005. Besides, the leaf 0xC0000005 does not contain cache line size information. Signed-off-by: AlanSong <AlanSong-oc@zhaoxin.com>
…azui Signed-off-by: AlanSong <AlanSong-oc@zhaoxin.com>
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Add Zhaoxin support for RDRAND/RDSEED/ADX/SHA/AVX2 feature and fix detecting cache line size for VIA processor in cpu.cpp.
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