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Codecov Report❌ Patch coverage is Additional details and impacted files@@ Coverage Diff @@
## main #116 +/- ##
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- Coverage 94.40% 94.23% -0.17%
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Files 44 43 -1
Lines 5681 5727 +46
Branches 5681 5727 +46
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+ Hits 5363 5397 +34
- Misses 245 253 +8
- Partials 73 77 +4
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Bencher Report| Branch | spoutn1k/EHT-1238-explode-metrics |
| Testbed | ci-runner |
Click to view all benchmark results
| Benchmark | Latency | Benchmark Result nanoseconds (ns) (Result Δ%) | Lower Boundary nanoseconds (ns) (Limit %) | Upper Boundary nanoseconds (ns) (Limit %) |
|---|---|---|---|---|
| parse_benchmarks/combine_performance | 📈 view plot 🚷 view threshold | 130,160,000.00 ns(-61.63%)Baseline: 339,250,909.09 ns | -868,899,873.57 ns (-667.56%) | 1,547,401,691.75 ns (8.41%) |
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| Branch | spoutn1k/EHT-1238-explode-metrics |
| Testbed | ci-runner |
⚠️ WARNING: No Threshold found!Without a Threshold, no Alerts will ever be generated.
- Dr (reads)
- L1 Hits (hits)
- Dw (writes)
- LL Miss Rate (misses (%))
- Total read+write (reads/writes)
- I1mr (misses (reads))
- DLmr (misses (reads))
- DLmw (misses (writes))
- D1mr (misses (reads))
- ILmr (misses (reads))
- D1 Miss Rate (misses (%))
- RAM Hits (hits)
- D1mw (misses (writes))
- Estimated Cycles (cycles)
- L1 Hit Rate (hits (%))
- LL Hits (hits)
- LL Hit Rate (hits (%))
- LLd Miss Rate (misses (%))
- LLi Miss Rate (misses (%))
- I1 Miss Rate (misses (%))
- RAM Hit Rate (hits (%))
Click here to create a new Threshold
For more information, see the Threshold documentation.
To only post results if a Threshold exists, set the--ci-only-thresholdsflag.
Click to view all benchmark results
| Benchmark | D1 Miss Rate | misses (%) | D1mr | misses (reads) x 1e3 | D1mw | misses (writes) x 1e3 | DLmr | misses (reads) | DLmw | misses (writes) x 1e3 | Dr | reads x 1e6 | Dw | writes x 1e6 | Estimated Cycles | cycles x 1e6 | I1 Miss Rate | misses (%) | I1mr | misses (reads) x 1e3 | ILmr | misses (reads) | Instructions | Benchmark Result instructions x 1e6 (Result Δ%) | Lower Boundary instructions x 1e6 (Limit %) | Upper Boundary instructions x 1e6 (Limit %) | L1 Hit Rate | hits (%) | L1 Hits | hits x 1e6 | LL Hit Rate | hits (%) | LL Hits | hits x 1e3 | LL Miss Rate | misses (%) | LLd Miss Rate | misses (%) | LLi Miss Rate | misses (%) | RAM Hit Rate | hits (%) | RAM Hits | hits x 1e3 | Total read+write | reads/writes x 1e6 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| lustre_metrics::memory_benches::bench_encode_lustre_metrics with_setup:generate_records() | 📈 view plot | 0.92 % | 📈 view plot | 24.89 reads x 1e3 | 📈 view plot | 9.17 writes x 1e3 | 📈 view plot | 108.00 reads | 📈 view plot | 6.47 writes x 1e3 | 📈 view plot | 2.49 x 1e6 | 📈 view plot | 1.23 x 1e6 | 📈 view plot | 14.87 x 1e6 | 📈 view plot | 0.01 % | 📈 view plot | 1.01 reads x 1e3 | 📈 view plot | 850.00 reads | 📈 view plot 🚷 view threshold | 10.79 x 1e6(-30.92%)Baseline: 15.62 x 1e6 | 1.98 x 1e6 (18.36%) | 29.25 x 1e6 (36.88%) | 📈 view plot | 99.76 % | 📈 view plot | 14.47 x 1e6 | 📈 view plot | 0.19 % | 📈 view plot | 27.63 x 1e3 | 📈 view plot | 0.05 % | 📈 view plot | 0.18 % | 📈 view plot | 0.01 % | 📈 view plot | 0.05 % | 📈 view plot | 7.43 x 1e3 | 📈 view plot | 14.51 x 1e6 |
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| Branch | spoutn1k/EHT-1238-explode-metrics |
| Testbed | ci-runner |
⚠️ WARNING: No Threshold found!Without a Threshold, no Alerts will ever be generated.
- LLi Miss Rate (misses (%))
- LL Hit Rate (hits (%))
- L1 Hits (hits)
- LL Hits (hits)
- D1 Miss Rate (misses (%))
- LL Miss Rate (misses (%))
- D1mr (misses (reads))
- Dr (reads)
- I1 Miss Rate (misses (%))
- Total read+write (reads/writes)
- RAM Hits (hits)
- Estimated Cycles (cycles)
- D1mw (misses (writes))
- DLmw (misses (writes))
- I1mr (misses (reads))
- L1 Hit Rate (hits (%))
- DLmr (misses (reads))
- Dw (writes)
- LLd Miss Rate (misses (%))
- ILmr (misses (reads))
- RAM Hit Rate (hits (%))
Click here to create a new Threshold
For more information, see the Threshold documentation.
To only post results if a Threshold exists, set the--ci-only-thresholdsflag.
Click to view all benchmark results
| Benchmark | D1 Miss Rate | misses (%) | D1mr | misses (reads) x 1e3 | D1mw | misses (writes) x 1e3 | DLmr | misses (reads) | DLmw | misses (writes) x 1e3 | Dr | reads x 1e6 | Dw | writes x 1e6 | Estimated Cycles | cycles x 1e6 | I1 Miss Rate | misses (%) | I1mr | misses (reads) x 1e3 | ILmr | misses (reads) | Instructions | Benchmark Result instructions x 1e6 (Result Δ%) | Lower Boundary instructions x 1e6 (Limit %) | Upper Boundary instructions x 1e6 (Limit %) | L1 Hit Rate | hits (%) | L1 Hits | hits x 1e6 | LL Hit Rate | hits (%) | LL Hits | hits x 1e3 | LL Miss Rate | misses (%) | LLd Miss Rate | misses (%) | LLi Miss Rate | misses (%) | RAM Hit Rate | hits (%) | RAM Hits | hits x 1e3 | Total read+write | reads/writes x 1e6 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| lustre_metrics::memory_benches::bench_encode_lustre_metrics with_setup:generate_records() | 📈 view plot | 0.92 % | 📈 view plot | 24.95 reads x 1e3 | 📈 view plot | 8.92 writes x 1e3 | 📈 view plot | 114.00 reads | 📈 view plot | 6.46 writes x 1e3 | 📈 view plot | 2.47 x 1e6 | 📈 view plot | 1.23 x 1e6 | 📈 view plot | 14.81 x 1e6 | 📈 view plot | 0.01 % | 📈 view plot | 1.06 reads x 1e3 | 📈 view plot | 884.00 reads | 📈 view plot 🚷 view threshold | 10.75 x 1e6(-25.99%)Baseline: 14.52 x 1e6 | 2.19 x 1e6 (20.36%) | 26.86 x 1e6 (40.02%) | 📈 view plot | 99.76 % | 📈 view plot | 14.41 x 1e6 | 📈 view plot | 0.19 % | 📈 view plot | 27.48 x 1e3 | 📈 view plot | 0.05 % | 📈 view plot | 0.18 % | 📈 view plot | 0.01 % | 📈 view plot | 0.05 % | 📈 view plot | 7.46 x 1e3 | 📈 view plot | 14.44 x 1e6 |
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Contributor
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Is this needed for current release? If so, please rebase |
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spoutn1k
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jgrund
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