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Merged
serge-sans-paille merged 1 commit into from
Sep 12, 2025
Merged

Test and improve GCC support for riscv #1168

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28 changes: 14 additions & 14 deletions .github/workflows/cross-rvv.yml
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Original file line number Diff line number Diff line change
@@ -1,38 +1,38 @@
name: RISC-V RVV cross-compilation build
on: [push, pull_request]
concurrency:
group: ${{ github.workflow }}-${{ github.job }}-${{ github.ref }}
group: ${{ github.workflow }}-${{ matrix.sys.compiler }}-${{ github.ref }}
cancel-in-progress: true
env:
GCC_VERSION: "12"
jobs:
build:
runs-on: ubuntu-latest
name: 'RISC-V RVV${{ matrix.vector_bits }}'
strategy:
matrix:
sys:
- { compiler: 'gcc', gcc_runtime: '14'}
- { compiler: 'clang', version: '17', gcc_runtime: '14'}
- { compiler: 'clang', version: '18', gcc_runtime: '14'}
vector_bits:
- 128
- 256
- 512
LLVM_VERSION:
- 17
- 18
steps:
- name: Setup GCC
run: |
sudo apt-get -y -qq update
sudo apt-get -y -qq --no-install-suggests --no-install-recommends install gcc-${GCC_VERSION}-riscv64-linux-gnu g++-${GCC_VERSION}-riscv64-linux-gnu
sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-gcc riscv64-linux-gnu-gcc /usr/bin/riscv64-linux-gnu-gcc-${GCC_VERSION} 20
sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-g++ riscv64-linux-gnu-g++ /usr/bin/riscv64-linux-gnu-g++-${GCC_VERSION} 20
sudo apt-get -y -qq --no-install-suggests --no-install-recommends install gcc-${{ matrix.sys.gcc_runtime }}-riscv64-linux-gnu g++-${{ matrix.sys.gcc_runtime }}-riscv64-linux-gnu
sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-gcc riscv64-linux-gnu-gcc /usr/bin/riscv64-linux-gnu-gcc-${{ matrix.sys.gcc_runtime }} 20
sudo update-alternatives --install /usr/bin/riscv64-linux-gnu-g++ riscv64-linux-gnu-g++ /usr/bin/riscv64-linux-gnu-g++-${{ matrix.sys.gcc_runtime }} 20
- name: Setup LLVM
if: ${{ matrix.sys.compiler == 'clang' }}
run: |
# Install latest LLVM stable
# Install given LLVM version
curl -o llvm.sh https://apt.llvm.org/llvm.sh
chmod u+x llvm.sh
sudo ./llvm.sh ${{ matrix.LLVM_VERSION }}
sudo ln -srf $(which clang-${{ matrix.LLVM_VERSION }}) /usr/bin/clang
sudo ln -srf $(which clang++-${{ matrix.LLVM_VERSION }}) /usr/bin/clang++
sudo ./llvm.sh ${{ matrix.sys.version }}
sudo ln -srf $(which clang-${{ matrix.sys.version }}) /usr/bin/clang
sudo ln -srf $(which clang++-${{ matrix.sys.version }}) /usr/bin/clang++
rm llvm.sh
- name: Setup QEMU
uses: docker/setup-qemu-action@v3.0.0
Expand All @@ -53,7 +53,7 @@ jobs:
-DTARGET_ARCH=generic
-DCMAKE_C_FLAGS="-march=rv64gcv_zvl${{ matrix.vector_bits }}b_zba_zbb_zbs -mrvv-vector-bits=zvl"
-DCMAKE_CXX_FLAGS="-march=rv64gcv_zvl${{ matrix.vector_bits }}b_zba_zbb_zbs -mrvv-vector-bits=zvl"
-DCMAKE_TOOLCHAIN_FILE=${{ github.workspace }}/.github/toolchains/clang-riscv64-linux-gnu.cmake
-DCMAKE_TOOLCHAIN_FILE=${{ github.workspace }}/.github/toolchains/${{ matrix.sys.compiler }}-riscv64-linux-gnu.cmake
- name: Build
run: cmake --build _build
- name: Testing xsimd
Expand Down
71 changes: 40 additions & 31 deletions include/xsimd/types/xsimd_rvv_register.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -62,9 +62,12 @@ namespace xsimd
static constexpr size_t rvv_width_mf4 = XSIMD_RVV_BITS / 4;
static constexpr size_t rvv_width_mf2 = XSIMD_RVV_BITS / 2;
static constexpr size_t rvv_width_m1 = XSIMD_RVV_BITS;
static constexpr size_t rvv_width_m2 = XSIMD_RVV_BITS * 2;
static constexpr size_t rvv_width_m4 = XSIMD_RVV_BITS * 4;
static constexpr size_t rvv_width_m8 = XSIMD_RVV_BITS * 8;

// Cope with gcc limitation, see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116484
#define XSIMD_RVV_WIDTH_MF8 (XSIMD_RVV_BITS / 8)
#define XSIMD_RVV_WIDTH_MF4 (XSIMD_RVV_BITS / 4)
#define XSIMD_RVV_WIDTH_MF2 (XSIMD_RVV_BITS / 2)
#define XSIMD_RVV_WIDTH_M1 XSIMD_RVV_BITS

// rvv_type_info is a utility class to convert scalar type and
// bitwidth into rvv register types.
Expand All @@ -79,30 +82,30 @@ namespace xsimd
//
template <class T, size_t Width>
struct rvv_type_info;
#define XSIMD_RVV_MAKE_TYPE(scalar, t, s, vmul) \
template <> \
struct rvv_type_info<scalar, rvv_width_m1 * vmul> \
{ \
static constexpr size_t width = rvv_width_m1 * vmul; \
using type = XSIMD_RVV_TYPE(t, s, vmul); \
using byte_type = XSIMD_RVV_TYPE(u, 8, vmul); \
using fixed_type = type __attribute__((riscv_rvv_vector_bits(width))); \
template <class U> \
static XSIMD_INLINE type bitcast(U x) noexcept \
{ \
const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words); \
} \
template <> \
XSIMD_INLINE type bitcast<type>(type x) noexcept { return x; } \
template <class U> \
static XSIMD_INLINE byte_type as_bytes(U x) noexcept \
{ \
static_assert(std::is_same<U, type>::value, "inconsistent conversion types"); \
const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words); \
} \
};
#define XSIMD_RVV_MAKE_TYPE(scalar, t, s, vmul) \
template <> \
struct rvv_type_info<scalar, rvv_width_m1 * vmul> \
{ \
static constexpr size_t width = rvv_width_m1 * vmul; \
using type = XSIMD_RVV_TYPE(t, s, vmul); \
using byte_type = XSIMD_RVV_TYPE(u, 8, vmul); \
using fixed_type = type __attribute__((riscv_rvv_vector_bits(/*width=*/XSIMD_RVV_WIDTH_M1 * vmul))); \
template <class U> \
static XSIMD_INLINE type bitcast(U x) noexcept \
{ \
const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, t, s, m, vmul)(words); \
} \
template <class U> \
static XSIMD_INLINE byte_type as_bytes(U x) noexcept \
{ \
static_assert(std::is_same<U, type>::value, "inconsistent conversion types"); \
const auto words = XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, s, m, vmul)(x); \
return XSIMD_RVV_JOINT5(__riscv_vreinterpret_, u, 8, m, vmul)(words); \
} \
}; \
template <> \
XSIMD_INLINE XSIMD_RVV_TYPE(t, s, vmul) rvv_type_info<scalar, rvv_width_m1 * vmul>::bitcast<XSIMD_RVV_TYPE(t, s, vmul)>(XSIMD_RVV_TYPE(t, s, vmul) x) noexcept { return x; }

#define XSIMD_RVV_MAKE_TYPES(vmul) \
XSIMD_RVV_MAKE_TYPE(int8_t, i, 8, vmul) \
Expand Down Expand Up @@ -235,17 +238,17 @@ namespace xsimd
template <>
struct semitype<2>
{
using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(rvv_width_mf2)));
using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF2)));
};
template <>
struct semitype<4>
{
using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(rvv_width_mf4)));
using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF4)));
};
template <>
struct semitype<8>
{
using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(rvv_width_mf8)));
using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF8)));
};
using fixed_type = typename semitype<divisor>::type;
using super::as_bytes;
Expand Down Expand Up @@ -374,7 +377,7 @@ namespace xsimd
struct rvv_bool
{
using bool_info = rvv_bool_info<rvv_width_m1 * sizeof(T) * 8 / Width>;
using storage_type = vuint8m1_t __attribute__((riscv_rvv_vector_bits(rvv_width_m1)));
using storage_type = vuint8m1_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_M1)));
using type = typename bool_info::type;
storage_type value;
rvv_bool() = default;
Expand Down Expand Up @@ -489,6 +492,12 @@ namespace xsimd
using type = detail::rvv_bool_simd_register<T>;
};
} // namespace types

#undef XSIMD_RVV_WIDTH_MF8
#undef XSIMD_RVV_WIDTH_MF4
#undef XSIMD_RVV_WIDTH_MF2
#undef XSIMD_RVV_WIDTH_M1

#else
using rvv = detail::rvv<0xFFFFFFFF>;
#endif
Expand Down