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Merged
serge-sans-paille merged 2 commits into from
Dec 30, 2025
Merged

Feature/restore riscv support #1239

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1b3e69d
[ci] Fix RISCV recipe
serge-sans-paille Dec 30, 2025
545a791
Fix RISCV build
serge-sans-paille Dec 30, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/cross-rvv.yml
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
name: RISC-V RVV cross-compilation build
on: [push, pull_request]
concurrency:
group: ${{ github.workflow }}-${{ matrix.sys.compiler }}-${{ github.ref }}
group: ${{ github.workflow }}-${{ github.job }}-${{ github.ref }}
cancel-in-progress: true
jobs:
build:
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4 changes: 2 additions & 2 deletions include/xsimd/arch/xsimd_rvv.hpp
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Expand Up @@ -513,7 +513,7 @@ namespace xsimd
return __riscv_vset(tmp, 1, hi);
}

template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int>::type = 0> D_INLINE rvv_reg_t<T, W * 2> rvvabut(rvv_reg_t<T, W> const& lo, rvv_reg_t<T, W> const& hi) noexcept
template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int> = 0> XSIMD_INLINE rvv_reg_t<T, W * 2> rvvabut(rvv_reg_t<T, W> const& lo, rvv_reg_t<T, W> const& hi) noexcept
{
return __riscv_vslideup(lo, hi, lo.vl, lo.vl * 2);
}
Expand All @@ -538,7 +538,7 @@ namespace xsimd
typename rvv_reg_t<T, W>::register_type tmp = vv;
return tmp;
}
template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int>::type = 0> reg_t<T, W> rvvget_hi(rvv_reg_t<T, W * 2> const& vv) noexcept
template <class T, size_t W, std::enable_if_t<W<types::detail::rvv_width_m1, int> = 0> rvv_reg_t<T, W> rvvget_hi(rvv_reg_t<T, W * 2> const& vv) noexcept
{
return __riscv_vslidedown(vv, vv.vl / 2, vv.vl);
}
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62 changes: 27 additions & 35 deletions include/xsimd/types/xsimd_rvv_register.hpp
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Expand Up @@ -219,6 +219,25 @@ namespace xsimd
type get() const { return value; }
void set(type v) { value = v; }
};

template <size_t div>
struct semitype;
template <>
struct semitype<2>
{
using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF2)));
};
template <>
struct semitype<4>
{
using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF4)));
};
template <>
struct semitype<8>
{
using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF8)));
};

//
// But sometimes we want our storage type to be less than a whole
// register, while presenting as a whole register to the outside
Expand All @@ -233,53 +252,26 @@ namespace xsimd
using super = rvv_type_info<T, rvv_width_m1>;
static constexpr size_t width = rvv_width_m1 / divisor;
using typename super::type;
template <size_t div>
struct semitype;
template <>
struct semitype<2>
{
using type = vuint8mf2_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF2)));
};
template <>
struct semitype<4>
{
using type = vuint8mf4_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF4)));
};
template <>
struct semitype<8>
{
using type = vuint8mf8_t __attribute__((riscv_rvv_vector_bits(XSIMD_RVV_WIDTH_MF8)));
};
using fixed_type = typename semitype<divisor>::type;
using super::as_bytes;
using super::bitcast;

fixed_type value;
template <size_t div>
vuint8m1_t get_bytes() const;
template <>
vuint8m1_t get_bytes<2>() const { return __riscv_vlmul_ext_v_u8mf2_u8m1(value); }
template <>
vuint8m1_t get_bytes<4>() const { return __riscv_vlmul_ext_v_u8mf4_u8m1(value); }
template <>
vuint8m1_t get_bytes<8>() const { return __riscv_vlmul_ext_v_u8mf8_u8m1(value); }
vuint8m1_t get_bytes(std::integral_constant<size_t, 2>) const { return __riscv_vlmul_ext_v_u8mf2_u8m1(value); }
vuint8m1_t get_bytes(std::integral_constant<size_t, 4>) const { return __riscv_vlmul_ext_v_u8mf4_u8m1(value); }
vuint8m1_t get_bytes(std::integral_constant<size_t, 8>) const { return __riscv_vlmul_ext_v_u8mf8_u8m1(value); }
type get() const noexcept
{
vuint8m1_t bytes = get_bytes<divisor>();
vuint8m1_t bytes = get_bytes(std::integral_constant<size_t, divisor>());
return bitcast(bytes);
}
template <size_t div>
void set_bytes(vuint8m1_t);
template <>
void set_bytes<2>(vuint8m1_t v) { value = __riscv_vlmul_trunc_v_u8m1_u8mf2(v); }
template <>
void set_bytes<4>(vuint8m1_t v) { value = __riscv_vlmul_trunc_v_u8m1_u8mf4(v); }
template <>
void set_bytes<8>(vuint8m1_t v) { value = __riscv_vlmul_trunc_v_u8m1_u8mf8(v); }
void set_bytes(vuint8m1_t v, std::integral_constant<size_t, 2>) { value = __riscv_vlmul_trunc_v_u8m1_u8mf2(v); }
void set_bytes(vuint8m1_t v, std::integral_constant<size_t, 4>) { value = __riscv_vlmul_trunc_v_u8m1_u8mf4(v); }
void set_bytes(vuint8m1_t v, std::integral_constant<size_t, 8>) { value = __riscv_vlmul_trunc_v_u8m1_u8mf8(v); }
void set(type v)
{
vuint8m1_t bytes = as_bytes(v);
set_bytes<divisor>(bytes);
set_bytes(bytes, std::integral_constant<size_t, divisor>());
}
};
template <class T>
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