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Adhere to Verilog convention Test #11: Commit 4a00577 pushed by yliu-hashed
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Compile and Release Package Compile and Release Package #13: Manually run by yliu-hashed
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Compile and Release Package Compile and Release Package #9: Manually run by yliu-hashed
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Add datasheet entries for display Test #10: Commit 70a39f1 pushed by yliu-hashed
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Update module shape image display Test #9: Commit cfa497d pushed by yliu-hashed
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Replace multiple subst with patsubst Test #8: Commit 5a26c7b pushed by yliu-hashed
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Add a ASCII display module Test #7: Commit 0cd9e18 pushed by yliu-hashed
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Fix add sources as test dependencies Test #6: Commit 0ae114f pushed by yliu-hashed
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Improve sequential multiplication Test #5: Commit 0d54de8 pushed by yliu-hashed
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Fix mul_seq.v cycle printing length on error Test #4: Commit 7c39797 pushed by yliu-hashed
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Convert synth rules to use wildcard Test #3: Commit 7ef93ce pushed by yliu-hashed
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Restructure Makefile Test #2: Commit c4962c0 pushed by yliu-hashed
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Add testing action on github Test #1: Commit 2557221 pushed by yliu-hashed
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v0.1.0 Compile and Release Package #8: Release v0.1.0 created by yliu-hashed
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Compile and Release Package Compile and Release Package #7: Manually run by yliu-hashed
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