Drc lvs fixes

.cockpitrc

@@ -1,6 +1,6 @@
 [cockpit]
   # Do not change this section
-  config = 2025-1
+  config = 2025-2
 
   # Still Work in Progress
 
@@ -24,6 +24,7 @@
   #                   ixc013g2_iocell_rev1.2.0
   #                   ixc013g2_iocell_rev1.2.1
   #                   open_io_v0.1
+  #                   open_io_v0.2
   #   bondpad       : bondpad_70x70_v0
   #
   #   STD cell      : ixc013g2ng_stdcell_rev0.0.4
@@ -51,15 +52,20 @@
 
   libs    = SG13G2_1.3.1 \
             open_stdcell_v3.2 \
-            open_io_v0.1 \ 
+            open_io_v0.2 \ 
             open_sram_v2.1
 
 
   # send an e-mail to <dz@ethz.ch> to ask for macros. Currently available
   # macro datasheets are available under:
   #   /usr/pack/ihp-sg13-kgf/open_ihp_sg13g2/IHP-Open-PDK-main_v2.0/sg13g2_sram
 
-  macros  = RM_IHPSG13_1P_256x64_c2_bm_bist
+  macros  = RM_IHPSG13_1P_1024x64_c2_bm_bist \
+            RM_IHPSG13_1P_2048x64_c2_bm_bist \
+            RM_IHPSG13_1P_256x48_c2_bm_bist \
+            RM_IHPSG13_1P_256x64_c2_bm_bist \
+            RM_IHPSG13_1P_512x64_c2_bm_bist \
+            RM_IHPSG13_1P_64x64_c2_bm_bist
 
 
 [version]
@@ -81,7 +87,7 @@
   innovus   =  innovus-21
   dfii      =  ic-6
   calibre   =  calibre-2021.3
-  oseda     =  oseda -2025.01
+  oseda     =  oseda -2025.07
 
 [command]
   # Startup commands available through the GUI buttons.
@@ -99,8 +105,8 @@
   innovus                      =  xterm -g 136x40 -T innovus-21.13 -e "cds_innovus-21.13.000 innovus"
   calibre                      =  xterm -g 120x40 -T calibredrv-2021.3 -e "./start_calibre 2021.3"
   dfii                         =  ./start_dfii
-  yosys                        =  xterm -g 120x40 -T yosys -e "oseda -2025.01 yosys"
-  openroad                     =  xterm -g 120x40 -T openroad -e "oseda -2025.01 openroad -gui"
-  klayout                      =  xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.01 klayout -e"
+  yosys                        =  xterm -g 120x40 -T yosys -e "oseda -2025.07 yosys -C"
+  openroad                     =  xterm -g 120x40 -T openroad -e "oseda -2025.07 openroad -gui"
+  klayout                      =  xterm -g 120x40 -T klayout -e "setenv KLAYOUT_HOME ./.klayout; oseda -2025.07 klayout -e"
   dz:llama                     = llama
 

.github/scripts/check_sim.sh

@@ -12,6 +12,7 @@ expected_lines=(
   "\[JTAG\] Halting hart 0"
   "\[JTAG\] Resumed hart 0"
   "\[UART\] Hello World!"
+  "\[UART\] Loopback received: internal msg"
   "\[UART\] Result: 0x8940, Cycles: 0xBD"
   "\[UART\] Tick"
   "\[UART\] Tock"

.github/workflows/artistic.yml

@@ -77,7 +77,7 @@ jobs:
       - name: Install packages in OSEDA
         uses: ./.github/actions/oseda-cmd
         with:
-          cmd: "pip install gdspy"
+          cmd: "pip install --break-system-packages gdspy"
       - name: Meercat setup, export top-level GDS
         uses: ./.github/actions/oseda-cmd
         with:

.github/workflows/short-flow.yml

@@ -35,7 +35,7 @@ jobs:
         uses: actions/upload-artifact@v4
         with:
           name: croc-waveform
-          path: croc.vcd
+          path: croc.fst
         continue-on-error: true
 
       - name: Upload simulation output

Bender.local

@@ -4,7 +4,7 @@ overrides:
   common_cells: { path: "rtl/common_cells" }
   apb: { path: "rtl/apb" }
   register_interface: { path: "rtl/register_interface" }
-  apb_uart: { path: "rtl/apb_uart" }
+  obi_peripherals: { path: "rtl/obi_uart" }
   ibex: { path: "rtl/ibex" }
   obi: { path: "rtl/obi" }
   riscv-dbg: { path: "rtl/riscv-dbg" }

Bender.lock

@@ -6,14 +6,6 @@ packages:
       Path: rtl/apb
     dependencies:
     - common_cells
-  apb_uart:
-    revision: null
-    version: null
-    source:
-      Path: rtl/apb_uart
-    dependencies:
-    - apb
-    - register_interface
   common_cells:
     revision: null
     version: null
@@ -42,6 +34,14 @@ packages:
     dependencies:
     - common_cells
     - common_verification
+  obi_peripherals:
+    revision: null
+    version: null
+    source:
+      Path: rtl/obi_uart
+    dependencies:
+    - common_cells
+    - obi
   register_interface:
     revision: null
     version: null

Bender.yml

@@ -16,8 +16,8 @@ dependencies:
   register_interface:   { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.1  }
   apb:                  { git: "https://github.com/pulp-platform/apb.git",                  version: 0.2.4  }
   timer_unit:           { git: "https://github.com/pulp-platform/timer_unit.git",           version: 1.0.3  }
-  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.3  }
-  apb_uart:             { git: "https://github.com/pulp-platform/apb_uart.git",             version: 0.2.1  }
+  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.7  }
+  obi_peripherals:      { git: "https://github.com/pulp-platform/obi_peripherals.git",      rev: 21ee04d    } # UART
   cve2:                 { path: "rtl/cve2" } # a vendor package (no Bender.yml), see below 
 
 
@@ -167,15 +167,13 @@ vendor_package:
       - { from: 'Bender.yml',         to: 'Bender.yml',     patch_dir: '' }
       - { from: 'doc/timer_unit.pdf', to: 'timer_unit.pdf', patch_dir: 'doc/' }
 
-  - name: apb_uart
-    target_dir: rtl/apb_uart
-    upstream: { git: "https://github.com/pulp-platform/apb_uart.git", rev: "6c7dde3d749ac8274377745c105da8c8b8cd27c6"  } # v0.2.1
-    patch_dir: "rtl/patches/apb_uart"
-    exclude_from_upstream:
-      - "src/vhdl_orig"
+  - name: obi_peripherals
+    target_dir: rtl/obi_uart
+    upstream: { git: "https://github.com/pulp-platform/obi_peripherals.git", rev: "21ee04d267025f6ea3d2faa462272287ddcb9bbb"  } # newest
+    patch_dir: "rtl/patches/obi_uart"
     mapping:
-      - { from: 'src/',        to: '',            patch_dir: 'src/' }
-      - { from: 'Bender.yml',  to: 'Bender.yml',  patch_dir: '' }
+      - { from: 'hw/obi_uart/', to: '',            patch_dir: 'hw/' }
+      - { from: 'Bender.yml',   to: 'Bender.yml',  patch_dir: '' }
 
 
   #########

CHANGELOG.md

@@ -7,6 +7,27 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.1.0/),
 and this project loosely follows to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 
+## 1.2.0 - 2025-07-11
+
+### Added
+
+- hw: replace apb_uart with new obi_uart
+- test: add UART loopback mode in helloworld.c
+
+### Changed
+
+- tools: update to version 2025.07.pre1
+- pdk: update cockpitrc (ETHZ internal use)
+- tools: change verilator tracing from vcd to fst
+- openroad: allow congestion in incremental global route
+
+### Fixed
+
+- openroad: fix min-area violations caused by extract_parasitics
+- sw: fix 'relocation truncated to fit' linker error
+- ci: fix pip install for ubuntu-latest in CI
+
+
 ## 1.1.0 - 2025-05-07
 
 ### Added
@@ -42,6 +63,7 @@ and this project loosely follows to [Semantic Versioning](https://semver.org/spe
 - verilator: speedup compile and synthesis
 - bender: fix cve2 vendor dependency
 
+
 ## 1.0.0 - 2024-12-05
 
 ### Added

Makefile

@@ -88,16 +88,21 @@ vsim-yosys: vsim/compile_netlist.tcl $(SW_HEX) yosys/out/croc_chip_yosys_debug.v
 
 
 # Verilator
-VERILATOR_ARGS  = --binary -j 0 -Wno-fatal
-VERILATOR_ARGS += -Wno-style -Wno-WIDTHEXPAND
-VERILATOR_ARGS += --timing --autoflush --trace --trace-structs
+# Turn off style warnings and well-defined SystemVerilog warnings that should be part of -Wno-style
+VERILATOR_ARGS = -Wno-fatal -Wno-style \
+	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
+
+VERILATOR_ARGS += --binary -j 0
+VERILATOR_ARGS += --timing --autoflush --trace-fst --trace-threads 2 --trace-structs
 VERILATOR_ARGS +=  --unroll-count 1 --unroll-stmts 1
+VERILATOR_ARGS += --x-assign fast --x-initial fast
+VERILATOR_CFLAGS += -O3 -march=native -mtune=native
 
 verilator/croc.f: Bender.lock Bender.yml
 	$(BENDER) script verilator -t rtl -t verilator -DSYNTHESIS -DVERILATOR > $@
 
 verilator/obj_dir/Vtb_croc_soc: verilator/croc.f $(SW_HEX)
-	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 -CFLAGS "-O1 -march=native" --top tb_croc_soc -f croc.f
+	cd verilator; $(VERILATOR) $(VERILATOR_ARGS) -O3 --top tb_croc_soc -f croc.f
 
 ## Simulate RTL using Verilator
 verilator: verilator/obj_dir/Vtb_croc_soc

README.md

@@ -6,7 +6,7 @@ As it is oriented towards education, it forgoes some configurability to increase
 
 Croc is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.
 
-Croc was sucesfully taped out in Nov 2024. The chip is called [MLEM](http://asic.ee.ethz.ch/2024/MLEM.html), named after the sound Yoshi makes when eating a tasty fruit.
+Croc was successfully taped out in Nov 2024. The chip is called [MLEM](http://asic.ee.ethz.ch/2024/MLEM.html), named after the sound Yoshi makes when eating a tasty fruit.
 MLEM was designed and prepared for tapeout by ETHZ students as a bachelor project. The exact code and scripts used for the tapeout can be seen in the frozen [mlem-tapeout](https://github.com/pulp-platform/croc/tree/mlem-tapeout) branch.
 
 
@@ -39,7 +39,7 @@ The main SoC configurations are in `rtl/croc_pkg.sv`:
 | `BankNumWords`      | `512`            | Number of 32bit words in a memory bank                |
 | `NumSramBanks`      | `2`              | Number of memory banks                                |
 
-The SRAMs are instantiated via a technology wrapper called `tc_sram` (tc: tech_cells), the technology-independent implementation is in `rtl/tech_cells_generic/tc_sram.sv`. A number of SRAM configurations are implemented using IHP130 SRAM memories in `ihp13/tc_sram.sv`. If an unimplemented SRAM configuration is instantiated it will result in a `tc_sram_blackbox` module which can then be easily identified from the synthesis results.
+The SRAMs are instantiated via a technology wrapper called `tc_sram_impl` (tc: tech_cells), the technology-independent implementation is in `rtl/tech_cells_generic/tc_sram_impl.sv`. A number of SRAM configurations are implemented using IHP130 SRAM memories in `ihp13/tc_sram_impl.sv`. If an unimplemented SRAM configuration is instantiated it will result in a `tc_sram_blackbox` module which can then be easily identified from the synthesis results.
 
 ## Bootmodes
 

croc.flist

@@ -91,27 +91,16 @@ rtl/common_cells/stream_arbiter.sv
 rtl/common_cells/stream_omega_net.sv
 rtl/common_cells/mem_to_banks.sv
 rtl/apb/apb_pkg.sv
-rtl/register_interface/reg_intf.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
-rtl/register_interface/periph_to_reg.sv
-rtl/register_interface/reg_to_apb.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
-rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
-rtl/apb_uart/slib_clock_div.sv
-rtl/apb_uart/slib_counter.sv
-rtl/apb_uart/slib_edge_detect.sv
-rtl/apb_uart/slib_fifo.sv
-rtl/apb_uart/slib_input_filter.sv
-rtl/apb_uart/slib_input_sync.sv
-rtl/apb_uart/slib_mv_filter.sv
-rtl/apb_uart/uart_baudgen.sv
-rtl/apb_uart/uart_interrupt.sv
-rtl/apb_uart/uart_receiver.sv
-rtl/apb_uart/uart_transmitter.sv
-rtl/apb_uart/apb_uart.sv
-rtl/apb_uart/apb_uart_wrap.sv
-rtl/apb_uart/reg_uart_wrap.sv
+rtl/obi/obi_pkg.sv
+rtl/obi/obi_intf.sv
+rtl/obi/obi_rready_converter.sv
+rtl/obi/obi_atop_resolver.sv
+rtl/obi/obi_cut.sv
+rtl/obi/obi_demux.sv
+rtl/obi/obi_err_sbr.sv
+rtl/obi/obi_mux.sv
+rtl/obi/obi_sram_shim.sv
+rtl/obi/obi_xbar.sv
 rtl/cve2/cve2_pkg.sv
 rtl/cve2/cve2_alu.sv
 rtl/cve2/cve2_compressed_decoder.sv
@@ -132,16 +121,21 @@ rtl/cve2/cve2_id_stage.sv
 rtl/cve2/cve2_prefetch_buffer.sv
 rtl/cve2/cve2_if_stage.sv
 rtl/cve2/cve2_core.sv
-rtl/obi/obi_pkg.sv
-rtl/obi/obi_intf.sv
-rtl/obi/obi_rready_converter.sv
-rtl/obi/obi_atop_resolver.sv
-rtl/obi/obi_cut.sv
-rtl/obi/obi_demux.sv
-rtl/obi/obi_err_sbr.sv
-rtl/obi/obi_mux.sv
-rtl/obi/obi_sram_shim.sv
-rtl/obi/obi_xbar.sv
+rtl/obi_uart/obi_uart_pkg.sv
+rtl/obi_uart/obi_uart_baudgen.sv
+rtl/obi_uart/obi_uart_interrupts.sv
+rtl/obi_uart/obi_uart_modem.sv
+rtl/obi_uart/obi_uart_rx.sv
+rtl/obi_uart/obi_uart_tx.sv
+rtl/obi_uart/obi_uart_register.sv
+rtl/obi_uart/obi_uart.sv
+rtl/register_interface/reg_intf.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_arb.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_ext.sv
+rtl/register_interface/periph_to_reg.sv
+rtl/register_interface/reg_to_apb.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg_shadow.sv
+rtl/register_interface/lowrisc_opentitan/prim_subreg.sv
 rtl/riscv-dbg/dm_pkg.sv
 rtl/riscv-dbg/debug_rom/debug_rom.sv
 rtl/riscv-dbg/debug_rom/debug_rom_one_scratch.sv

docker-compose.yml

@@ -7,7 +7,7 @@
 
 services:
   pulp-docker:
-    image: hpretl/iic-osic-tools:2025.03
+    image: hpretl/iic-osic-tools:2025.07.pre1
     environment:
       - UID=${UID}
       - GID=${GID}

ethz.env

@@ -7,9 +7,9 @@
 # - Philippe Sauter <phsauter@iis.ee.ethz.ch>
 
 # used in Makefiles
-export BENDER="oseda bender"
-export OPENROAD="oseda openroad"
-export KLAYOUT="oseda klayout"
-export YOSYS="oseda yosys"
-export PYTHON3="oseda python3"
-export VERILATOR="oseda verilator"
+export BENDER="oseda -2025.07 bender"
+export OPENROAD="oseda -2025.07 openroad"
+export KLAYOUT="oseda -2025.07 klayout"
+export YOSYS="oseda -2025.07 yosys"
+export PYTHON3="oseda -2025.07 python3"
+export VERILATOR="oseda -2025.07 verilator"

klayout/def2gds.sh

@@ -11,14 +11,23 @@ cd $klayout_dir
 ################
 ### project  ###
 ################
-topcell="croc_chip"
-defpath="$root_dir/openroad/out/croc.def"
+top_design=${TOP_DESIGN:-"croc_chip"}
+def_path=${DEF_PATH:-"$root_dir/openroad/out/croc.def"}
 
 
 ################
 ## technology ##
 ################
-if [[ -f "$root_dir/cockpit.log" ]]; then
+tech="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt"
+layer="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp"
+
+# create klayout home dir and add pdk to path
+export KLAYOUT_HOME="$klayout_dir/.klayout"
+export KLAYOUT_PATH="$(realpath $root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout):$KLAYOUT_PATH"
+mkdir -p $KLAYOUT_HOME/tech
+
+
+if [[ -d "$root_dir/technology" ]]; then
     echo "Init tech from ETHZ DZ cockpit"
     pdk_dir=$(realpath "$root_dir/technology")
     pdk_cells_lef_dir="${pdk_dir}/lef"
@@ -52,13 +61,8 @@ gds="$(find "$pdk_cells_gds_dir" -name 'sg13g2_stdcell.gds' -exec realpath {} \;
      $(find "$pdk_io_gds_dir" -name 'sg13g2_io.gds' -exec realpath {} \;) \
      $(find "$bondpad_gds_dir" -name '*.gds' -exec realpath {} \;)"
 
-tech="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyt"
-layer="$root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout/tech/sg13g2.lyp"
 
-# create klayout home dir and add pdk to path
-export KLAYOUT_HOME="$klayout_dir/.klayout"
-export KLAYOUT_PATH="$(realpath $root_dir/ihp13/pdk/ihp-sg13g2/libs.tech/klayout):$KLAYOUT_PATH"
-mkdir -p $KLAYOUT_HOME/tech
+ln -sfr $klayout_dir/sg13g2.map $KLAYOUT_HOME/tech/sg13g2.map
 
 # all <lef-files> entries for the tech file
 lef_files=""
@@ -68,15 +72,15 @@ done
 
 # replace the placeholder tag with the real lef files
 sed "/<lef-files><\/lef-files>/c $lef_files" "$tech" > $KLAYOUT_HOME/tech/sg13g2.lyt
-ln -sfr $klayout_dir/sg13g2.map $KLAYOUT_HOME/tech/sg13g2.map
 
 echo "$gds" > $KLAYOUT_HOME/tech/tech_gds.f
 
+
 klayout_cmd="$KLAYOUT -zz \
-          -rd design_name=\"$topcell\" \
-          -rd in_def=\"$defpath\" \
+          -rd design_name=\"$top_design\" \
+          -rd in_def=\"$def_path\" \
           -rd gds_flist=\"$KLAYOUT_HOME/tech/tech_gds.f\" \
-          -rd out_file=\"${topcell}.gds\" \
+          -rd out_file=\"${top_design}.gds\" \
           -rd tech_file=\"$KLAYOUT_HOME/tech/sg13g2.lyt\" \
           -rd layer_map=\"$KLAYOUT_HOME/tech/sg13g2.map\" \
           -rm def2stream.py"