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[acc] Adds support for direct bignum load/store#252
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Signed-off-by: Hoang Nguyen Hien Pham <hien@zerorisc.com>
Signed-off-by: Hoang Nguyen Hien Pham <hien@zerorisc.com>
Signed-off-by: Hoang Nguyen Hien Pham <hien@zerorisc.com>
Expanded the bn.xid covergroup instruction encoding to include direct load and store instructions. Modified the register incrementing coverage cross to exclude the SPP field of encoding now that this is used to determine a bn.ld from bn.sd. Added RIG support for new instructions and included them in bad memory related generators. Signed-off-by: Evan Apinis <eapinis@zerorisc.com>
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Signed-off-by: Evan Apinis <eapinis@zerorisc.com>
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This PR adds a
BN.LDandBN.SDinstruction to the ACC bignum ISA to perform direct loads/stores between WDR and DMEM.BN.LDinstructions take two clock cycles whereasBN.SDtake only one. The instructions were implemented in RTL and the corresponding DV collateral was updated to support coverage collection and random assembly generation.