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Edits to fix int connections and vitis directives #37

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60b6c8b
Edits to fix int connections and vitis directives
narrucmot Aug 3, 2022
c265558
hdl: zub1cg_sbc_dualcam: fix PFM.AXI_PORTS declarations.
AlbertaBeef Aug 4, 2022
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121 changes: 87 additions & 34 deletions boards/zub1cg_sbc/dualcam/zub1cg_sbc_dualcam.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -102,21 +102,21 @@ proc avnet_add_user_io_preset {project projects_folder scriptdir} {

save_bd_design

#
# Vitis interrupt
#
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0
save_bd_design

apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { \
Clk_master {Auto} \
Clk_slave {Auto} \
Clk_xbar {Auto} \
Master {/zynq_ultra_ps_e_0/M_AXI_HPM0_FPD} \
Slave {/axi_intc_0/s_axi} \
ddr_seg {Auto} intc_ip {/axi_interconnect_0} \
master_apm {0}} [get_bd_intf_pins axi_intc_0/s_axi]
save_bd_design
#~ #
#~ # Vitis interrupt
#~ #
#~ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0
#~ save_bd_design

#~ apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { \
#~ Clk_master {Auto} \
#~ Clk_slave {Auto} \
#~ Clk_xbar {Auto} \
#~ Master {/zynq_ultra_ps_e_0/M_AXI_HPM0_FPD} \
#~ Slave {/axi_intc_0/s_axi} \
#~ ddr_seg {Auto} intc_ip {/axi_interconnect_0} \
#~ master_apm {0}} [get_bd_intf_pins axi_intc_0/s_axi]
#~ save_bd_design

#
# System peripherals interrupts
Expand Down Expand Up @@ -179,7 +179,7 @@ proc avnet_add_user_io_preset {project projects_folder scriptdir} {
connect_bd_net [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins clk_wiz_0/clk_in1]
connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq0]
connect_bd_net [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins xlconcat_0/In5]
connect_bd_net [get_bd_pins axi_intc_0/irq] [get_bd_pins xlconcat_0/In6]
#~ connect_bd_net [get_bd_pins axi_intc_0/irq] [get_bd_pins xlconcat_0/In6]
save_bd_design

connect_bd_net [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
Expand Down Expand Up @@ -277,20 +277,36 @@ proc avnet_add_vitis_directives {project projects_folder scriptdir} {

# define AXI ports
set_property PFM.AXI_PORT { \
M_AXI_HPM1_FPD {memport "M_AXI_GP"} \
S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "HPC0" memory "zynq_ultra_ps_e_0 HPC0_DDR_LOW"} \
S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "HPC1" memory "zynq_ultra_ps_e_0 HPC1_DDR_LOW"} \
S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0" memory "zynq_ultra_ps_e_0 HP0_DDR_LOW"} \
S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1" memory "zynq_ultra_ps_e_0 HP1_DDR_LOW"} \
S_AXI_HP2_FPD {memport "S_AXI_HP" sptag "HP2" memory "zynq_ultra_ps_e_0 HP2_DDR_LOW"} \
S_AXI_HP3_FPD {memport "S_AXI_HP" sptag "HP3" memory "zynq_ultra_ps_e_0 HP3_DDR_LOW"} \
} [get_bd_cells /zynq_ultra_ps_e_0]

set_property PFM.AXI_PORT { \
M03_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M04_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M05_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M06_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M07_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M08_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M09_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M10_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M11_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M12_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M13_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M14_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M15_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
M16_AXI {memport "M_AXI_GP" sptag "" memory "" is_range "false"} \
} [get_bd_cells /axi_interconnect_0]

# required for Vitis 2020.1
# reference : https://github.com/Xilinx/Vitis-In-Depth-Tutorial/blob/master/Vitis_Platform_Creation/Introduction/02-Edge-AI-ZCU104/step1.md
# define interrupt ports
set_property PFM.IRQ {intr {id 0 range 32}} [get_bd_cells /axi_intc_0]

#~ set_property PFM.IRQ {intr {id 0 range 32}} [get_bd_cells /axi_intc_0]
set_property PFM.IRQ {pl_ps_irq1 {id 0 range 7}} [get_bd_cells /zynq_ultra_ps_e_0]

# Set platform project properties
set_property platform.description "Base ZUBoard-1CG development platform" [current_project]
set_property platform.uses_pr false [current_project]
Expand Down Expand Up @@ -363,6 +379,9 @@ proc create_hier_cell_GPIO { parentCell nameHier } {
create_bd_pin -dir O -from 0 -to 0 trigger
create_bd_pin -dir O -from 0 -to 0 vpss_csc_resetn
create_bd_pin -dir O -from 0 -to 0 vpss_scaler_resetn
create_bd_pin -dir O -from 0 -to 0 rst
create_bd_pin -dir O -from 0 -to 0 stby

create_bd_pin -dir I -type clk clk100
create_bd_pin -dir O -from 0 -to 0 frame_buffer_rd_resetn
create_bd_pin -dir O -from 0 -to 0 frame_buffer_wr_resetn
Expand Down Expand Up @@ -421,20 +440,47 @@ proc create_hier_cell_GPIO { parentCell nameHier } {
CONFIG.DIN_WIDTH {8} \
CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_5]

# Create instance: xlslice_6, and set properties
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_6
set_property -dict [ list \
CONFIG.DIN_FROM {6} \
CONFIG.DIN_TO {6} \
CONFIG.DIN_WIDTH {8} \
CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_6]

# Create instance: xlslice_7, and set properties
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_7
set_property -dict [ list \
CONFIG.DIN_FROM {7} \
CONFIG.DIN_TO {7} \
CONFIG.DIN_WIDTH {8} \
CONFIG.DOUT_WIDTH {1}] [get_bd_cells xlslice_7]



# Create interface connections
connect_bd_intf_net [get_bd_intf_pins S_AXI] [get_bd_intf_pins axi_gpio_0/S_AXI]

# Create port connections
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_2/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din]
connect_bd_net [get_bd_pins clk100] [get_bd_pins axi_gpio_0/s_axi_aclk]
connect_bd_net [get_bd_pins s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn]
connect_bd_net [get_bd_pins trigger] [get_bd_pins xlslice_0/Dout]
connect_bd_net [get_bd_pins icp3_i2c_id_select] [get_bd_pins xlslice_1/Dout]
connect_bd_net [get_bd_pins sp3] [get_bd_pins xlslice_2/Dout]
connect_bd_net [get_bd_pins frame_buffer_wr_resetn] [get_bd_pins xlslice_3/Dout]
connect_bd_net [get_bd_pins frame_buffer_rd_resetn] [get_bd_pins xlslice_4/Dout]
connect_bd_net [get_bd_pins vpss_scaler_resetn] [get_bd_pins xlslice_5/Dout]
connect_bd_net [get_bd_pins vpss_csc_resetn] [get_bd_pins xlslice_4/Dout]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_0/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_1/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_2/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_3/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_4/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_5/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_6/Din]
connect_bd_net [get_bd_pins axi_gpio_0/gpio_io_o] [get_bd_pins xlslice_7/Din]
connect_bd_net [get_bd_pins xlslice_0/Dout] [get_bd_pins trigger]
connect_bd_net [get_bd_pins xlslice_1/Dout] [get_bd_pins icp3_i2c_id_select]
connect_bd_net [get_bd_pins xlslice_2/Dout] [get_bd_pins sp3]
connect_bd_net [get_bd_pins xlslice_3/Dout] [get_bd_pins frame_buffer_wr_resetn]
connect_bd_net [get_bd_pins xlslice_4/Dout] [get_bd_pins frame_buffer_rd_resetn]
connect_bd_net [get_bd_pins xlslice_4/Dout] [get_bd_pins vpss_csc_resetn]
connect_bd_net [get_bd_pins xlslice_5/Dout] [get_bd_pins vpss_scaler_resetn]
connect_bd_net [get_bd_pins xlslice_6/Dout] [get_bd_pins rst]
connect_bd_net [get_bd_pins xlslice_7/Dout] [get_bd_pins stby]

# Perform GUI Layout
regenerate_bd_layout -hierarchy [get_bd_cells /GPIO]
Expand Down Expand Up @@ -782,10 +828,10 @@ proc avnet_add_pl_dualcam {project projects_folder scriptdir} {

save_bd_design

create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1
set_property -dict [list CONFIG.NUM_PORTS {2}] [get_bd_cells xlconcat_1]
#~ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1
#~ set_property -dict [list CONFIG.NUM_PORTS {2}] [get_bd_cells xlconcat_1]

save_bd_design
#~ save_bd_design

# Create instance: CAPTURE_PIPELINE
create_hier_cell_CAPTURE_PIPELINE [current_bd_instance .] CAPTURE_PIPELINE
Expand Down Expand Up @@ -819,12 +865,16 @@ proc avnet_add_pl_dualcam {project projects_folder scriptdir} {
create_bd_port -dir O -from 0 -to 0 icp3_i2c_id_select
create_bd_port -dir O -from 0 -to 0 sp3
create_bd_port -dir O -from 0 -to 0 trigger
create_bd_port -dir O -from 0 -to 0 rst
create_bd_port -dir O -from 0 -to 0 stby

# GPIO - Create port connections
connect_bd_net [get_bd_pins clk_wiz_0/clk_out3] [get_bd_ports clk48m]
connect_bd_net [get_bd_pins GPIO/icp3_i2c_id_select] [get_bd_ports icp3_i2c_id_select]
connect_bd_net [get_bd_pins GPIO/sp3] [get_bd_ports sp3]
connect_bd_net [get_bd_pins GPIO/trigger] [get_bd_ports trigger]
connect_bd_net [get_bd_pins GPIO/rst] [get_bd_ports rst]
connect_bd_net [get_bd_pins GPIO/stby] [get_bd_ports stby]

save_bd_design

Expand All @@ -838,9 +888,12 @@ proc avnet_add_pl_dualcam {project projects_folder scriptdir} {
save_bd_design

# Interrupts - Create port connections
connect_bd_net [get_bd_pins CAPTURE_PIPELINE/csirxss_csi_irq] [get_bd_pins xlconcat_1/In0]
connect_bd_net [get_bd_pins CAPTURE_PIPELINE/interrupt] [get_bd_pins xlconcat_1/In1]
connect_bd_net [get_bd_pins xlconcat_1/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq1]
#~ connect_bd_net [get_bd_pins CAPTURE_PIPELINE/csirxss_csi_irq] [get_bd_pins xlconcat_1/In0]
#~ connect_bd_net [get_bd_pins CAPTURE_PIPELINE/interrupt] [get_bd_pins xlconcat_1/In1]
#~ connect_bd_net [get_bd_pins xlconcat_1/dout] [get_bd_pins zynq_ultra_ps_e_0/pl_ps_irq1]

connect_bd_net [get_bd_pins CAPTURE_PIPELINE/csirxss_csi_irq] [get_bd_pins xlconcat_0/In3]
connect_bd_net [get_bd_pins CAPTURE_PIPELINE/interrupt] [get_bd_pins xlconcat_0/In4]

connect_bd_net [get_bd_pins clk_wiz_0/clk_out5] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk]

Expand Down
6 changes: 6 additions & 0 deletions boards/zub1cg_sbc/dualcam/zub1cg_sbc_dualcam.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -20,16 +20,22 @@ set_property PACKAGE_PIN J2 [get_ports {trigger[0]}]; # HP_DP_13_GC_N
set_property PACKAGE_PIN J3 [get_ports {icp3_i2c_id_select[0]}]; # HP_DP_13_GC_P
set_property PACKAGE_PIN N3 [get_ports {sp3[0]}]; # HP_SE_01
set_property PACKAGE_PIN L3 [get_ports clk48m]; # HP_DP_12_GC_N
set_property PACKAGE_PIN C3 [get_ports {rst[0]}]; # HP_DP_22_N
set_property PACKAGE_PIN L4 [get_ports {stby[0]}]; # HP_DP_12_GC_P

set_property IOSTANDARD LVCMOS12 [get_ports {icp3_i2c_id_select[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {sp3[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {trigger[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports clk48m]
set_property IOSTANDARD LVCMOS12 [get_ports {rst[0]}]
set_property IOSTANDARD LVCMOS12 [get_ports {stby[0]}]

set_property DRIVE 8 [get_ports {icp3_i2c_id_select[0]}]
set_property DRIVE 8 [get_ports {sp3[0]}]
set_property DRIVE 8 [get_ports {trigger[0]}]
set_property DRIVE 8 [get_ports clk48m]
set_property DRIVE 8 [get_ports {rst[0]}]
set_property DRIVE 8 [get_ports {stby[0]}]

#
# ISP I2C & SPI
Expand Down