Add CI linting, JLCPCB rule parity, and KiCad version/docs refresh - #31
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July 1, 2026 11:36
Adds tools/lint_dru.py (no dependencies, Python 3.8+) and a GitHub Actions
workflow that runs it on any change to a .kicad_dru file. The linter catches
the mistake classes that have actually reached this repo before:
- unbalanced parentheses / malformed s-expressions
- missing or wrong (version 1) header
- a rule with no name or no constraint
- duplicate rule names
- rule names not prefixed with the fab name
- lowercase item-type literals ('track'/'via'/'pad'...) that KiCad expects in
PascalCase and that otherwise silently never match
Both existing rule files pass.
JLCPCB.kicad_dru quoted these three specs in TODO comments but never implemented them, while the refactored PCBWay file now has equivalents. Implements them from JLCPCB's own quoted capabilities and removes the TODOs: - JLCPCB: Plated Slot Width (min 0.5mm) - JLCPCB: Non-Plated Slot Width (min 1.0mm) - JLCPCB: NPTH to Copper (non-Track) (min 0.2mm) Brings the two fab rule sets to structural parity.
- Note the rules are authored for KiCad 8 syntax and forward-compatible with KiCad 9 and 10 (all tokens unchanged; 9/10 only add constraints). - Add a Validation section covering tools/lint_dru.py and headless kicad-cli pcb drc, and link the KiCad CLI reference.
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Jul 1, 2026
Replaces the hand-maintained JLCPCB.kicad_dru / PCBWay.kicad_dru (with their error-prone 'Choose between' comment blocks) with concrete files generated per build variant from capabilities/<FAB>.toml by tools/generate_dru.py. - capabilities/JLCPCB.toml, capabilities/PCBWay.toml: values + variants + flags, seeded from the previous committed rules. - tools/generate_dru.py: emits one .kicad_dru per variant (default variant keeps the plain <FAB>.kicad_dru name); --check fails if committed output drifts. - Generated matrix: 2L-1oz, 4L-1oz (default), 4L-2oz, 6L-1oz per fab. - Every file gains impedance-controlled net classes (50R, 60R/90R/100R/120R_Diff) with typical starting values and a stackup-dependency warning. - JLCPCB gains the NPTH-to-Copper (non-Track) rule, which #31's message listed but never actually landed in the file. - lint_dru.py: derive the fab prefix from the part before the first '-'. - CI: run the generator --check before linting. Generated defaults are rule-for-rule equivalent to the previous files (bar the removed comment alternates and the additive net-class/NPTH-copper rules).
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Three pieces of maintenance work.
1. CI validation (new)
There was no automated check on the rule files, so a regression like the lowercase-
'track'conditions fixed in #29 could merge unnoticed.tools/lint_dru.py— dependency-free Python linter that flags: unbalanced parens / malformed s-expressions, missing(version 1)header, a rule with no name or no constraint, duplicate rule names, wrong fab prefix, and lowercase item-type literals ('track'/'via'/'pad'/...) that KiCad silently never matches..github/workflows/lint.yml— runs it on any change to a.kicad_drufile..kicad_druvalidator (kicad-cli pcb drcneeds a board), so this fills a real gap.2. JLCPCB rule parity with PCBWay
JLCPCB.kicad_druquoted three specs in TODO comments but never implemented them, while the refactored PCBWay file (#29) now has equivalents. Implemented from JLCPCB's own quoted capabilities and removed the TODOs:JLCPCB: Plated Slot Width(min 0.5mm)JLCPCB: Non-Plated Slot Width(min 1.0mm)JLCPCB: NPTH to Copper (non-Track)(min 0.2mm)3. Docs / KiCad version refresh
KiCad 8 is now two majors behind (9 shipped Feb 2025, 10 shipped March 2026). Verified against the KiCad parser source that the
.kicad_drusyntax used here is unchanged across 8 → 9 → 10 (those releases only add constraints likecreepage). README now:tools/lint_dru.pyand headlesskicad-cli pcb drc.Note on the capability audit (the "verify rule values against current fab specs" task)
This was requested but could not be completed in this environment: the egress policy blocks
jlcpcb.com,pcbway.com, and the Wayback Machine (403 at the proxy), so the live capability pages can't be fetched for verbatim values. I won't change numeric limits based on unverified search summaries. One item worth a manual check: search summaries suggest PCBWay's plated-hole-to-trace minimum may be 0.35mm vs the currentPCBWay: PTH to Tracerule at 0.33mm — verify against the live page before adjusting. To do the full audit, either allowlist those domains for the session or paste the capability tables and I'll extract exact values.Generated by Claude Code