Uart rx

[patrickerich]

Please consider merging in these changes.

There are 2 commits:

1. Updates the arty a7 config file
   • Replaces some deprecated statements
   • Adds an (optional) switch for using an arty a7-100t board (instead of the default a7-35t board).
2. Adds RX functionality to the UART.
   • Updates both the hardware and the software.
   • The demo has been updated to (optionally) echo the RX data to the TX data (this is the default).
   • An addtional python file (using pyserial) is included to test the super-system echoing the RX input.

Possible point of attention:
In the software there is a 'circular include'. super_system includes uart and uart includes super_system.
This is not an issue because of the ifndef guards., but I am unsure if this is acceptable.

Tested set of commands to verify the functionality of this commit:

rm -rf build
rm -rf sw/build/
(cd sw && mkdir -p build && cd build && cmake ../ && make)
fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:super_system --part xc7a100tcsg324-1
make -C ./build/lowrisc_ibex_super_system_0/synth-vivado/ pgm
./util/load_super_system.sh run ./sw/build/demo/demo
python ./sw/demo/uart_hello.py

NOTES:

1. This is for an Arty-A7-100T board. For an Arty A7-35T board, don't include "--part xc7a100tcsg324-1"
2. At the moment Fusesoc cannot be used directly for programming the FPGA. This is replaced with "make -C ./build/lowrisc_ibex_super_system_0/synth-vivado/ pgm". A pull request to fix this issue can be found here: Restore Vivado run_main method; fixes #317 olofk/edalize#319

[patrickerich]

Since commiting the PR I have 2 more items that may be interesting enough to add:

1. A working cocotb_test (pytest) simulation setup (with verilator) that uses the cocotbext-uart module for simulating the UART.

2. A simple (functional and easily extensible) command-interpreter example program (via the UART).

Both these items require the RX functionality from this PR. Can I add these items to this PR or should I open a separate PR for these items (or wait until this PR has been considered)?

---

Some more details on these 2 items:

1. Pytest/cocotb_test simulation setup

   • Uses a fusesoc verilator sim target for setting up the simulation (and creating the EDAM file). Requires some minor changes to exisitng core files (but not in the vendor directory!). The SRAMInitFile parameter can be specified with the fusesoc command.
   • Requires some additional python packages to be installed.
   • Requires a "slightly patched" verilator installation for cocotb (tested to work with the most recent verilator version).
   • Uses a custom python "cocotb bridge" class to extract all required information from the EDAM data created by Fusesoc.

2. Uart command interpreter example

   • Does not use an interrupt for incoming RX data (like the demo modification in this PR).
   • Is a "blocking" command interpreter that uses an 'EOT' character to signify the end of a command/data transfer.
   • Uses some standard C library functions (like strtok, strcmp, itoa, atoi, etc)
   • Includes a simple command-line python application for automatically setting up the connection (e.g. scanning for a specific ID) and handling the communication (e.g. adding and removing the additional EOT character).

[GregAC]

Hi @patrickerich thanks for this. My apologies for letting it sit here for several months but the good news is I'm wanting to merge it. I've recently renamed super system to 'Ibex Demo System' and it's become a repository under the lowRISC organization. The PR adding your work to Ibex Demo System is here: lowRISC/ibex-demo-system#4. I've made some changes in a separate commit that's part of that PR. Ordinarily I'd review and we'd iterate towards a final version but given the length of time I've left it I felt it was better for me to just make the changes I wanted.

[patrickerich]

Hi @GregAC thanks for letting me know. I will update to the 'Ibex Demo System' soon. I may have some other interesting stuff to contribute as well.