• 🎓 Final Year Student — Electronics & VLSI Design and Technology
• 🏫 Bangalore Institute of Technology, Bangalore
• 💡 Passionate about RTL Design, Digital Systems & Chip Architecture
• 🔭 Currently exploring RTL Design & VLSI Architectures
• 📫 Reach me at: theppss3006@gmail.com

• ✅ Cache Memory Architecture
• ✅ FSM Design
• ✅ Digital VLSI Design Flow
• ✅ Embedded Systems & IoT
• ✅ SRAM / DRAM Interfaces

📍 Miyapur, Hyderabad | ⏳ Ongoing (6 Months)

• Executing digital design and hardware modeling using Verilog HDL
• Implementing sequential logic circuits — flip-flops, shift registers, counters, frequency dividers
• Developing testbenches for functional verification and logic debugging
• Hands-on exposure to VLSI-based logic design workflows

Major Project 2025-26 | IoT + VLSI Design

• Hardware: ESP32, IR Sensor, Load Cell, DC Motor, Water Pump
• VLSI: Feeding Timer Module in Verilog HDL, verified using Cadence
• Features: Telegram Bot notifications, real-time monitoring
• Results: Power ≈ 4.2 µW, Timing Slack +6933 ps ✅
• Tools: Verilog, Cadence Virtuoso, Arduino IDE

Mini Project 2024-25 | Memory Architecture

• Implemented: Direct, 2-Way, 4-Way, 8-Way set associative mapping
• Features: Configurable Way Controller Unit, Hit/Miss detection
• Memory: 512KB Cache ↔ 512MB Main Memory, 64B block size
• Tools: Verilog HDL, Xilinx ISE