Cache Memory Design Using Verilog HDL 🧠

Design and simulation of a configurable Cache Memory system implementing multiple mapping techniques using Verilog HDL and Xilinx ISE.

Bangalore Institute of Technology | Mini Project 2024-25
Domain: Digital Design & Memory Architecture
Tools: Verilog HDL, Xilinx ISE

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📌 Overview

This project implements a Cache Memory System in Verilog HDL that supports multiple mapping techniques. The design bridges the performance gap between the CPU and main memory by implementing efficient cache architecture with configurable mapping modes controlled by a Way Controller Unit.

Memory	Size
Main Memory	512 MB
Cache Memory	512 KB
Block Size	64 Bytes
CPU Address Width	29 bits

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🏗️ Architecture

CPU Address [28:0]
        │
        ▼
┌───────────────────┐
│  Way Controller   │  ← way_control[1:0]
│       Unit        │
└─────────┬─────────┘
          │
    ┌─────┴──────┐
    │  Mapping   │
    │  Selection │
    └─────┬──────┘
          │
  ┌───────┼───────────┐
  │       │           │
Direct   2-Way      4-Way    8-Way
Mapping  Mapping   Mapping  Mapping
512KB    2×256KB   4×128KB  8×64KB

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🔀 Mapping Techniques

Way Controller Truth Table

Way Control Bits	Cache Mode	Cache Size per Set
00	Direct Mapping	512 KB (single bank)
01	2-Way Set Associative	256 KB × 2 sets
10	4-Way Set Associative	128 KB × 4 sets
11	8-Way Set Associative	64 KB × 8 sets

Address Breakdown (Direct Mapping)

Bits	Field	Description
[28:19]	Tag bits	Identifies main memory block
[18:6]	Cache Index	Selects cache line
[5:0]	Offset	Byte within cache block

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⚙️ Design Features

• ✅ Configurable mapping via Way Controller Unit
• ✅ Direct Mapping — fast, simple, single comparison
• ✅ 2-Way Set Associative — reduced conflict misses
• ✅ 4-Way Set Associative — balanced performance
• ✅ 8-Way Set Associative — highest hit rate
• ✅ Hit/Miss detection logic
• ✅ Read/Write enable control
• ✅ Reset functionality
• ✅ Simulated and verified with Xilinx ISE waveforms

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📊 Results

All four mapping configurations were successfully simulated and verified:

Mapping	RTL Verified	Waveform Verified
Direct Mapping	✅	✅
2-Way Mapping	✅	✅
4-Way Mapping	✅	✅
8-Way Mapping	✅	✅

Simulation results demonstrated reduced memory access latency and optimized hit rates across all mapping configurations.

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🛠️ Tools Used

• Language: Verilog HDL
• Tool: Xilinx ISE Design Suite
• Simulation: Xilinx ISim
• University: Bangalore Institute of Technology (VTU)

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📁 Repository Contents

File	Description
Mini_project_report.pdf	Complete project report

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🔮 Future Work

1. Extend to multi-level cache (L1, L2, L3)
2. Implement advanced replacement policies (LFU, ML-based)
3. Add ECC (Error Correcting Code) for data integrity
4. Energy-efficient implementation using gated clocking
5. Parameterized Verilog for dynamic cache configuration

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👩‍💻 Authors

Smriti Subramaniam (1BI22VL047)
Thanishqka P (1BI22VL051)

• 🎓 B.E. Electronics Engineering (VLSI Design & Technology)
• 🏫 Bangalore Institute of Technology, Bangalore
• 📧 theppss3006@gmail.com
• 🔗 GitHub

Guide: Mrs. Lavanya Y S, Asst. Professor, Dept. of EE(VDT), BIT

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📄 License

This project was developed for academic purposes at Bangalore Institute of Technology under Visvesvaraya Technological University (VTU), 2024-25.