V7 subsystem

Documentation/fpga/xrt.rst

@@ -275,7 +275,7 @@ fpga_bridge and fpga_region for the next region in the chain.
 fpga_bridge
 -----------
 
-Like the fpga_region, a fpga_bridge is created by walking the device tree
+Like the fpga_region, an fpga_bridge is created by walking the device tree
 of the parent group. The bridge is used for isolation between a parent and
 its child.
 
@@ -416,7 +416,7 @@ xclbin is compiled by end user using
 `Vitis <https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html>`_
 tool set from Xilinx. The xclbin contains sections describing user compiled
 acceleration engines/kernels, memory subsystems, clocking information etc. It also
-contains a FPGA bitstream for the user partition, UUIDs, platform name, etc.
+contains an FPGA bitstream for the user partition, UUIDs, platform name, etc.
 
 
 .. _xsabin_xclbin_container_format:

drivers/clk/Kconfig

@@ -384,5 +384,6 @@ source "drivers/clk/ti/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 source "drivers/clk/x86/Kconfig"
 source "drivers/clk/zynqmp/Kconfig"
+source "drivers/clk/xrt/Kconfig"
 
 endif

drivers/clk/Makefile

@@ -121,6 +121,7 @@ obj-y					+= versatile/
 ifeq ($(CONFIG_COMMON_CLK), y)
 obj-$(CONFIG_X86)			+= x86/
 endif
+obj-$(CONFIG_XRT_CLK_WIZ)		+= xrt/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_COMMON_CLK_ZYNQMP)         += zynqmp/

drivers/clk/xrt/Kconfig

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config XRT_CLK_WIZ
+	tristate "Clock driver for Xilinx Alveo clocking wizard"
+	depends on FPGA_XRT_LIB
+	select XRT_CLK_FREQ
+	select XRT_CLK_UCS
+	help
+	  Select this option to enable the Alveo clock controller driver.
+
+config XRT_CLK_FREQ
+	tristate "Driver for Xilinx Alveo clock frequency counter"
+	depends on FPGA_XRT_LIB
+	depends on XRT_CLK_WIZ
+	help
+	  Select this option to enable the Alveo clock frequency counter driver.
+
+config XRT_CLK_UCS
+	tristate "Driver for Xilinx Alveo user clock subsystem controller"
+	depends on FPGA_XRT_LIB
+	depends on XRT_CLK_WIZ
+	help
+	  Select this option to enable the Alveo user clock subsystem controller driver.

drivers/clk/xrt/Makefile

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for Xilinx Alveo clock devices
+#
+
+xrt-clock-objs			:= clock.o
+obj-$(CONFIG_XRT_CLK_WIZ)	+= xrt-clock.o
+
+xrt-clkfreq-objs		:= clkfreq.o
+obj-$(CONFIG_XRT_CLK_FREQ)	+= xrt-clkfreq.o
+
+xrt-ucs-objs			:= ucs.o
+obj-$(CONFIG_XRT_CLK_UCS)	+= xrt-ucs.o

drivers/fpga/xrt/lib/xleaf/clkfreq.c → drivers/clk/xrt/clkfreq.c

@@ -8,14 +8,14 @@
  *      Lizhi Hou<Lizhi.Hou@xilinx.com>
  */
 
-#include <linux/mod_devicetable.h>
+#include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/regmap.h>
 #include <linux/io.h>
-#include "metadata.h"
-#include "xleaf.h"
-#include "xleaf/clkfreq.h"
+#include <linux/xrt/metadata.h>
+#include <linux/xrt/xleaf.h>
+#include <linux/xrt/xleaf/clkfreq.h>
 
 #define CLKFREQ_ERR(clkfreq, fmt, arg...)   \
 	xrt_err((clkfreq)->xdev, fmt "\n", ##arg)
@@ -209,15 +209,26 @@ static struct xrt_dev_endpoints xrt_clkfreq_endpoints[] = {
 	{ 0 },
 };
 
+static const struct xrt_device_id xrt_clkfreq_ids[] = {
+	{ XRT_SUBDEV_CLKFREQ },
+	{ }
+};
+MODULE_DEVICE_TABLE(xrt, xrt_clkfreq_ids);
+
 static struct xrt_driver xrt_clkfreq_driver = {
 	.driver = {
 		.name = XRT_CLKFREQ,
+		.owner = THIS_MODULE,
 	},
+	.id_table = xrt_clkfreq_ids,
 	.subdev_id = XRT_SUBDEV_CLKFREQ,
 	.endpoints = xrt_clkfreq_endpoints,
 	.probe = clkfreq_probe,
 	.remove = clkfreq_remove,
 	.leaf_call = xrt_clkfreq_leaf_call,
 };
+module_xrt_driver(xrt_clkfreq_driver);
 
-XRT_LEAF_INIT_FINI_FUNC(clkfreq);
+MODULE_AUTHOR("XRT Team <runtime@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx XRT clock frequency counter driver");
+MODULE_LICENSE("GPL v2");

drivers/fpga/xrt/lib/xleaf/clock.c → drivers/clk/xrt/clock.c

@@ -10,15 +10,15 @@
  *      David Zhang <davidzha@xilinx.com>
  */
 
-#include <linux/mod_devicetable.h>
+#include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/regmap.h>
 #include <linux/io.h>
-#include "metadata.h"
-#include "xleaf.h"
-#include "xleaf/clock.h"
-#include "xleaf/clkfreq.h"
+#include <linux/xrt/metadata.h>
+#include <linux/xrt/xleaf.h>
+#include <linux/xrt/xleaf/clock.h>
+#include <linux/xrt/xleaf/clkfreq.h>
 
 /* XRT_CLOCK_MAX_NUM_CLOCKS should be a concept from XCLBIN_ in the future */
 #define XRT_CLOCK_MAX_NUM_CLOCKS	4
@@ -638,15 +638,26 @@ static struct xrt_dev_endpoints xrt_clock_endpoints[] = {
 	{ 0 },
 };
 
+static const struct xrt_device_id xrt_clock_ids[] = {
+	{ XRT_SUBDEV_CLOCK },
+	{ }
+};
+MODULE_DEVICE_TABLE(xrt, xrt_clock_ids);
+
 static struct xrt_driver xrt_clock_driver = {
 	.driver = {
 		.name = XRT_CLOCK,
+		.owner = THIS_MODULE,
 	},
+	.id_table = xrt_clock_ids,
 	.subdev_id = XRT_SUBDEV_CLOCK,
 	.endpoints = xrt_clock_endpoints,
 	.probe = clock_probe,
 	.remove = clock_remove,
 	.leaf_call = xrt_clock_leaf_call,
 };
+module_xrt_driver(xrt_clock_driver);
 
-XRT_LEAF_INIT_FINI_FUNC(clock);
+MODULE_AUTHOR("XRT Team <runtime@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx XRT clock driver");
+MODULE_LICENSE("GPL v2");

drivers/fpga/xrt/lib/xleaf/ucs.c → drivers/clk/xrt/ucs.c

@@ -8,14 +8,14 @@
  *      Lizhi Hou<Lizhi.Hou@xilinx.com>
  */
 
-#include <linux/mod_devicetable.h>
+#include <linux/module.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/regmap.h>
 #include <linux/io.h>
-#include "metadata.h"
-#include "xleaf.h"
-#include "xleaf/clock.h"
+#include <linux/xrt/metadata.h>
+#include <linux/xrt/xleaf.h>
+#include <linux/xrt/xleaf/clock.h>
 
 #define UCS_ERR(ucs, fmt, arg...)   \
 	xrt_err((ucs)->xdev, fmt "\n", ##arg)
@@ -139,14 +139,26 @@ static struct xrt_dev_endpoints xrt_ucs_endpoints[] = {
 	{ 0 },
 };
 
+static const struct xrt_device_id xrt_ucs_ids[] = {
+	{ XRT_SUBDEV_UCS },
+	{ }
+};
+MODULE_DEVICE_TABLE(xrt, xrt_ucs_ids);
+
 static struct xrt_driver xrt_ucs_driver = {
 	.driver = {
 		.name = XRT_UCS,
+		.owner = THIS_MODULE,
 	},
+	.id_table = xrt_ucs_ids,
 	.subdev_id = XRT_SUBDEV_UCS,
 	.endpoints = xrt_ucs_endpoints,
 	.probe = ucs_probe,
 	.leaf_call = xrt_ucs_leaf_call,
 };
 
-XRT_LEAF_INIT_FINI_FUNC(ucs);
+module_xrt_driver(xrt_ucs_driver);
+
+MODULE_AUTHOR("XRT Team <runtime@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx XRT user clock subsystem controller driver");
+MODULE_LICENSE("GPL v2");

drivers/fpga/xrt/include/group.h

@@ -9,7 +9,7 @@
 #ifndef _XRT_GROUP_H_
 #define _XRT_GROUP_H_
 
-#include "xleaf.h"
+#include <linux/xrt/xleaf.h>
 
 /*
  * Group driver leaf calls.

drivers/fpga/xrt/include/xroot.h

@@ -9,13 +9,10 @@
 #ifndef _XRT_ROOT_H_
 #define _XRT_ROOT_H_
 
-#include "xdevice.h"
-#include "subdev_id.h"
-#include "events.h"
-
-typedef bool (*xrt_subdev_match_t)(enum xrt_subdev_id, struct xrt_device *, void *);
-#define XRT_SUBDEV_MATCH_PREV	((xrt_subdev_match_t)-1)
-#define XRT_SUBDEV_MATCH_NEXT	((xrt_subdev_match_t)-2)
+#include <linux/xrt/xdevice.h>
+#include <linux/xrt/subdev_id.h>
+#include <linux/xrt/events.h>
+#include <linux/xrt/xleaf.h>
 
 /*
  * Root calls.

drivers/fpga/xrt/lib/Makefile

@@ -17,14 +17,8 @@ xrt-lib-objs :=			\
 	subdev.o		\
 	cdev.o			\
 	group.o			\
-	xleaf/vsec.o		\
 	xleaf/axigate.o		\
-	xleaf/devctl.o		\
-	xleaf/icap.o		\
-	xleaf/clock.o		\
-	xleaf/clkfreq.o		\
-	xleaf/ucs.o		\
-	xleaf/ddr_calibration.o
+	xleaf/icap.o
 
 ccflags-y := -I$(FULL_XRT_PATH)/include	 \
 	-I$(FULL_DTC_PATH)

drivers/fpga/xrt/lib/cdev.c

@@ -8,7 +8,7 @@
  *	Cheng Zhen <maxz@xilinx.com>
  */
 
-#include "xleaf.h"
+#include <linux/xrt/xleaf.h>
 #include "lib-drv.h"
 
 #define XRT_CDEV_DIR		"xrt"

drivers/fpga/xrt/lib/group.c

@@ -9,10 +9,11 @@
  */
 
 #include <linux/mod_devicetable.h>
-#include "xleaf.h"
-#include "subdev_pool.h"
+#include <linux/kmod.h>
+#include <linux/xrt/xleaf.h>
+#include <linux/xrt/metadata.h>
 #include "group.h"
-#include "metadata.h"
+#include "subdev_pool.h"
 #include "lib-drv.h"
 
 #define XRT_GRP "xrt_group"
@@ -136,6 +137,9 @@ static int xrt_grp_create_leaves(struct xrt_group *xg)
 	xrt_info(xg->xdev, "bringing up leaves...");
 	memcpy(grp_dtb, pdata->xsp_dtb, mlen);
 	for (did = 0; did < XRT_SUBDEV_NUM; did++) {
+		ret = xrt_drv_get(did);
+		if (ret)
+			continue;
 		eps = xrt_drv_get_endpoints(did);
 		while (eps && eps->xse_names) {
 			char *dtb = NULL;
@@ -169,6 +173,7 @@ static int xrt_grp_create_leaves(struct xrt_group *xg)
 			vfree(dtb);
 			/* Continue searching for the same instance from grp_dtb. */
 		}
+		xrt_drv_put(did);
 	}
 
 	xg->leaves_created = true;