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Fix logic for switching between virtual and main target address during Private Write #51

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Fix logic for switching between virtual and main target address during Private Write #51

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d3abb98
recovery_receiver: do not jump to Error state on address change
kgugala May 12, 2026
45f40ca
test_recovery: uncomment take_bus_control
kgugala May 12, 2026
3234f63
Update recovery_receiver waivers to match RTL change
robertszczepanski May 14, 2026
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10 changes: 8 additions & 2 deletions src/recovery/recovery_receiver.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -786,13 +786,19 @@ module recovery_receiver
TxDesc: begin
tx_pec_soft_rst_n_o = 1'b1;

if (bus_stop_i || other_target_start_i || (virtual_target_start_i && !bus_addr_i[0])) begin
if (bus_stop_i || (virtual_target_start_i && !bus_addr_i[0])) begin
// Protocol errors:
// - STOP instead of Sr (incomplete read transaction)
// - Sr + Addr to different target (abandoned our transaction)
// - Sr + Addr+W (expected read but got write)
unsupported_err = unsupported_err_det_en_i;
state_d = Error;
end else if (other_target_start_i) begin
unsupported_err = unsupported_err_det_en_i;
// - Sr + Addr to different target (abandoned our transaction)
// We can switch to our regular target, so we're not jumping to the Error state
// Error state keeps the width converter in soft reset, preventing any
// data to enter RX FIFO. To prevent loosing this data we jump to Done.
state_d = Done;
end else if (tx_desc_ready_i) begin
state_d = TxLenL;
tx_pec_enable_o = 1'b1;
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2 changes: 1 addition & 1 deletion verification/cocotb/top/lib_i3c_top/test_recovery.py
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Expand Up @@ -5389,7 +5389,7 @@ async def test_ri_read_interrupted_by_ccc(dut):
# uncommented, the controller sends actual S + Addr+W + CMD + PEC + Sr, in that case
# the recovery_receiver enters Error state and keeps RX Queue in soft reset state
# which blocks it from receiving data sent to main target on I3C bus.
# await i3c_controller.take_bus_control()
await i3c_controller.take_bus_control()

# Start RI write phase: S + Addr+W (to virtual target)
await i3c_controller.send_start()
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8 changes: 4 additions & 4 deletions verification/waivers/exclusion.yaml
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Expand Up @@ -3663,7 +3663,7 @@ exclusions:
branch:
- 17: [7] # unique case (state_q)
line:
- 1143 # unique case (state_q)
- 1149 # unique case (state_q)

Read only interface:
cond:
Expand All @@ -3681,17 +3681,17 @@ exclusions:

This would require controller to send Sr while target is in PP mode which is illegal:
line:
- 810 # TxDesc: state_d = Done; // Controller aborted read via Sr
- 816 # TxDesc: state_d = Done; // Controller aborted read via Sr
branch:
- 3: # unique case (state_q)
- 41 # TxDesc: if (bus_rstart_i) begin
- 42 # TxDesc: if (bus_rstart_i) begin
cond:
- 40: [2 "01"] # if ((tx_data_ready_i && tx_data_valid_o) || bus_rstart_i) begin

Not needed else:
branch:
- 3: # unique case (state_q)
- 52 # TxData: if (tx_data_valid_o) begin
- 53 # TxData: if (tx_data_valid_o) begin

Upper bits of a counter:
toggle:
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