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Add support for initializing DAT/DCT memories #6

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b7d78d5
Read DAT/DCT memories only on valid state
robertszczepanski Oct 22, 2025
43b2677
Add support for initializing memories
robertszczepanski Oct 22, 2025
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48 changes: 32 additions & 16 deletions src/hci/dxt.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -49,6 +49,9 @@ module dxt
logic [DatAw-1:0] dat_index_sw;
logic dat_word_index_sw;

logic dat_rd_req;
logic dat_wr_req;

logic dat_rd_ack;
logic dat_wr_ack;

Expand Down Expand Up @@ -99,25 +102,30 @@ module dxt
if (~rst_ni) begin
csr_dat_hwif_o.rd_data <= '0;
end else begin
case (dat_word_index_sw)
1'd0: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[31:0];
1'd1: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[63:32];
default: csr_dat_hwif_o.rd_data <= '0;
endcase
if (dat_mem_src_i.rvalid)
case (dat_word_index_sw)
1'd0: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[31:0];
1'd1: csr_dat_hwif_o.rd_data <= dat_mem_src_i.rdata[63:32];
default: csr_dat_hwif_o.rd_data <= '0;
endcase
else csr_dat_hwif_o.rd_data <= '0;
end
end

assign dat_rd_req = csr_dat_hwif_i.req & ~csr_dat_hwif_i.req_is_wr & ~dat_read_valid_hw_i;
assign dat_wr_req = csr_dat_hwif_i.req & csr_dat_hwif_i.req_is_wr;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
dat_rd_ack <= 1'b0;
dat_wr_ack <= 1'b0;
csr_dat_hwif_o.rd_ack <= 1'b0;
csr_dat_hwif_o.wr_ack <= 1'b0;
end else begin
dat_rd_ack <= csr_dat_hwif_i.req & ~csr_dat_hwif_i.req_is_wr & ~dat_read_valid_hw_i;
dat_rd_ack <= dat_rd_req;
csr_dat_hwif_o.rd_ack <= dat_rd_ack;

dat_wr_ack <= csr_dat_hwif_i.req & csr_dat_hwif_i.req_is_wr;
dat_wr_ack <= dat_wr_req;
csr_dat_hwif_o.wr_ack <= dat_wr_ack;
end
end
Expand All @@ -131,6 +139,9 @@ module dxt
logic [DctAw-1:0] dct_index_sw;
logic [1:0] dct_word_index_sw;

logic dct_rd_req;
logic dct_wr_req;

logic dct_rd_ack;
logic dct_wr_ack;

Expand Down Expand Up @@ -165,27 +176,32 @@ module dxt
if (~rst_ni) begin
csr_dct_hwif_o.rd_data <= '0;
end else begin
case (dct_word_index_sw)
2'd0: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[31:0];
2'd1: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[63:32];
2'd2: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[95:64];
2'd3: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[127:96];
default: csr_dct_hwif_o.rd_data <= '0;
endcase
if (dct_mem_src_i.rvalid)
case (dct_word_index_sw)
2'd0: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[31:0];
2'd1: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[63:32];
2'd2: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[95:64];
2'd3: csr_dct_hwif_o.rd_data <= dct_mem_src_i.rdata[127:96];
default: csr_dct_hwif_o.rd_data <= '0;
endcase
else csr_dct_hwif_o.rd_data <= '0;
end
end

assign dct_rd_req = csr_dct_hwif_i.req & ~csr_dct_hwif_i.req_is_wr & ~dct_read_valid_hw_i;
assign dct_wr_req = csr_dct_hwif_i.req & csr_dct_hwif_i.req_is_wr;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
dct_rd_ack <= 1'b0;
dct_wr_ack <= 1'b0;
csr_dct_hwif_o.rd_ack <= 1'b0;
csr_dct_hwif_o.wr_ack <= 1'b0;
end else begin
dct_rd_ack <= csr_dct_hwif_i.req & ~csr_dct_hwif_i.req_is_wr & ~dct_read_valid_hw_i;
dct_rd_ack <= dct_rd_req;
csr_dct_hwif_o.rd_ack <= dct_rd_ack;
// ACK write requests to remove CPU stall, even though they're illegal to DCT
dct_wr_ack <= csr_dct_hwif_i.req & csr_dct_hwif_i.req_is_wr;
dct_wr_ack <= dct_wr_req;
csr_dct_hwif_o.wr_ack <= dct_wr_ack;
end
end
Expand Down
11 changes: 8 additions & 3 deletions src/i3c_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,10 @@ module i3c_wrapper #(
parameter int unsigned DctAw = i3c_pkg::DctAw,

parameter int unsigned CsrAddrWidth = I3CCSR_pkg::I3CCSR_MIN_ADDR_WIDTH,
parameter int unsigned CsrDataWidth = I3CCSR_pkg::I3CCSR_DATA_WIDTH
parameter int unsigned CsrDataWidth = I3CCSR_pkg::I3CCSR_DATA_WIDTH,

parameter string DatMemInitFile = "",
parameter string DctMemInitFile = ""
) (
input clk_i, // clock
input rst_ni, // active low reset
Expand Down Expand Up @@ -242,7 +245,8 @@ module i3c_wrapper #(
prim_ram_1p_adv #(
.Depth(`DAT_DEPTH),
.Width(64),
.DataBitsPerMask(32)
.DataBitsPerMask(32),
.MemInitFile(DatMemInitFile)
) dat_memory (
.clk_i,
.rst_ni,
Expand All @@ -260,7 +264,8 @@ module i3c_wrapper #(
prim_ram_1p_adv #(
.Depth(`DCT_DEPTH),
.Width(128),
.DataBitsPerMask(32)
.DataBitsPerMask(32),
.MemInitFile(DctMemInitFile)
) dct_memory (
.clk_i,
.rst_ni,
Expand Down
6 changes: 3 additions & 3 deletions src/libs/mem/prim_generic_ram_1p.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ module prim_generic_ram_1p import prim_ram_1p_pkg::*; #(
end
end
end

// `include "prim_util_memload.svh"
// `endif
`ifndef SYNTHESIS
`include "caliptra_prim_util_memload.svh"
`endif
endmodule
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