arm64: dts: rockchip: add vpll clock parent for DP 4K overlay#490
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HeyMeco merged 1 commit intoMay 29, 2026
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The RK3576 has only one HDMI PHY PLL which is occupied by HDMI when both HDMI and DP are active. When the dp-4k overlay routes DP to VP0, the pixel clock falls back to gpll/cpll which can only provide ~396MHz via divider, far below the 533.25MHz needed for 3840x2160@60Hz. Set dclk_vp0_src parent to vpll. The VOP2 driver's rockchip_rk3576_drm_dclk_set_rate() will reprogram vpll to 1066.5MHz and divide by 2 to get the exact 533.25MHz pixel clock. Before: set dclk_vp0 to 533250000, get 396000000 After: set dclk_vp0 to 533250000, get 533250000 Signed-off-by: mingzq <north_sea@qq.com>
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Summary
dclk_vp0_srcparent tovpllin the recomputer-rk3576-devkit DP 4K overlay, enabling 4K@60Hz pixel clock support when DP is routed to VP0Problem
The RK3576 has only one HDMI PHY PLL which is occupied by HDMI when both HDMI and DP are active. When the dp-4k overlay routes DP to VP0, the pixel clock falls back to gpll/cpll which can only provide ~396MHz via divider, far below the 533.25MHz needed for 3840x2160@60Hz.
Before:
set dclk_vp0 to 533250000, get 396000000After:
set dclk_vp0 to 533250000, get 533250000Details
With this change, the VOP2 driver's
rockchip_rk3576_drm_dclk_set_rate()will reprogram vpll to 1066.5MHz and divide by 2 to get the exact 533.25MHz pixel clock.Test plan
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