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arm64: dts: rockchip: add vpll clock parent for DP 4K overlay #490

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Merged
HeyMeco merged 1 commit into from
May 29, 2026
Merged

arm64: dts: rockchip: add vpll clock parent for DP 4K overlay #490

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17 changes: 16 additions & 1 deletion arch/arm64/boot/dts/rockchip/overlay/recomputer-rk3576-devkit-dp-4k.dts
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Original file line number Diff line number Diff line change
@@ -1,12 +1,14 @@
/dts-v1/;
/plugin/;

#include <dt-bindings/clock/rockchip,rk3576-cru.h>

/ {
metadata {
title = "Route recomputer rk3576 devkit HDMI to VP1 and DP to VP0";
compatible = "seeed,recomputer rk3576 devkit";
category = "display";
description = "Switch display routing so HDMI uses VP1 and DP uses VP0.";
description = "Switch display routing so HDMI uses VP1 and DP uses VP0. Sets dclk_vp0_src parent to vpll for 4K@60Hz pixel clock support.";
};

fragment@0 {
Expand Down Expand Up @@ -69,4 +71,17 @@
target = <&vp1>;
__overlay__ { status = "okay"; };
};

/* Set dclk_vp0_src parent to vpll so DP on VP0 can achieve 4K@60Hz.
* Without this, DP falls back to gpll/cpll which can only provide
* ~396MHz (via divider), far below the 533.25MHz needed for 4K@60Hz.
* With vpll, the driver reprograms vpll to 1066.5MHz and divides by 2.
*/
fragment@11 {
target = <&vop>;
__overlay__ {
assigned-clocks = <&cru DCLK_VP0_SRC>;
assigned-clock-parents = <&cru PLL_VPLL>;
};
};
};
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