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I3C configuration.sv Coverage Gaps #199#192

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I3C configuration.sv Coverage Gaps #199#192
navadiya-cpu wants to merge 7 commits into
chipsalliance:v1p5from
navadiya-cpu:v1p5

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@navadiya-cpu

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I3C configuration.sv Coverage Gaps #199::

https://github.com/chipsalliance/caliptra-embargoed/issues/199#issuecomment-4246370051
Here are some scenarios I developed based on coverage gaps:

  1. test_bulk_interrupt_toggle
  2. test_interrupt_traffic_scenarios: comment out due to RTL limitations : Future fix
  3. test_specific_interrupt_force_001
  4. test_specific_interrupt_force_002
  5. test_specific_interrupt_force_003
  6. test_specific_interrupt_force_004
  7. test_specific_interrupt_force_005
  8. test_specific_interrupt_force_006
  9. test_specific_interrupt_force_007
  10. test_specific_interrupt_force_008

Signed-off-by: Ankita Navadiya <navadiya@google.com>
@linux-foundation-easycla

linux-foundation-easycla Bot commented Apr 21, 2026

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CLA Signed

The committers listed above are authorized under a signed CLA.

moidx
moidx previously approved these changes Apr 21, 2026
Comment thread verification/cocotb/top/lib_i3c_top/test_interrupt_toggles.py Outdated
@moidx moidx self-requested a review April 21, 2026 21:28
mkj121
mkj121 previously approved these changes Apr 22, 2026

@mkj121 mkj121 left a comment

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Possible tidy up in one comment

f_ena, f_force, f_sts = fields

# Ensure clean state: disable all interrupts and clear all status bits
await tb.write_csr(tb.reg_map.I3C_EC.TTI.INTERRUPT_ENABLE.base_addr, int2dword(0x00000000), 4)

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For consistency should all the interrupt force bits be cleared at this point too?

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Ensure all interrupt force bits are cleared at the end for a "clean state," preventing any impact on other tests.

Signed-off-by: Ankita Navadiya <navadiya@google.com>
@navadiya-cpu navadiya-cpu dismissed stale reviews from mkj121 and moidx via efd8960 April 22, 2026 19:26
Signed-off-by: Ankita Navadiya <navadiya@google.com>
Signed-off-by: Ankita Navadiya <navadiya@google.com>
@robertszczepanski

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Hi @navadiya-cpu,

Thanks for opening the PR.

Could you please explain the rationale behind using force/release here? As you wrote in the comment - those fields are either tied-off or masked. Shouldn't we simply waive this part?

@navadiya-cpu

navadiya-cpu commented May 7, 2026 via email

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4 participants