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feat(W47-RR): RBB RTL — OP_RBB=0xF1 controller, 37/37 assertions PASS#170

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feat(W47-RR): RBB RTL — OP_RBB=0xF1 controller, 37/37 assertions PASS#170
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Wave-47 Lane RR — RBB RTL (Reverse Body Bias Controller)

Context

SystemVerilog RTL for Wave-47 L-DPC34 Reverse Body Bias — generates V_BS = -V_DD·γ⁴ ≈ -2.5 mV bias on idle PE wells; decodes sacred opcode 0xF1 OP_RBB (first slot in EXTENDED sacred bank 0xD0..0xFF, R18 ceremony).

  • ONE SHOT: trinity-fpga#167
  • Coq SoT: t27#681 (trios-coq/Physics/RBB.v, 33 Qed)
  • Assertions JSON: trios#924 (31 IDs)
  • Rust witness: tt-trinity-max-true#44 (14/14 tests pass)

Files

File Lines Role
rtl/rbb/body_bias_gen.sv 63 Charge-pump stub, V_BS magnitude rail, band check, lock counter
rtl/rbb/rbb_controller.sv 138 Decodes 0xF1, drives V_BS, registered telemetry, R7 falsification gates, R18 bank witness
tb/rbb/tb_rbb.sv 158 37 SVA checks (off-state, engage, leak/overhead/net bands, freq invariance, TOPS/W lift, R18 extension, 16-opcode distinctness, disengage)

Verification

iverilog -g2012 -o /tmp/tb_rbb \
  rtl/rbb/body_bias_gen.sv rtl/rbb/rbb_controller.sv tb/rbb/tb_rbb.sv
vvp /tmp/tb_rbb
# → PASS=37 FAIL=0 — VERDICT: PASS

R-SI-1 Compliance (zero * operators)

body_bias_gen.sv:  0 `*` ops ✓
rbb_controller.sv: 0 `*` ops ✓

All multiplications pre-computed at elaboration:

  • LIFT_LHS_CONST = 20000 (= 1000 · (1063 - 1043))
  • LIFT_RHS_CONST = 15645 (= 15 · 1043)
  • Comparison 20000 ≥ 15645 ⇒ TOPS/W lift ≥ 1.5%

Cell Budget

Two combinational modules + ≤ 16 registers (lock counter + telemetry). Synthesis target ≤ 400 cells (W47 ONE SHOT cap).

Quantum Brain 1:1 Mapping

Layer Element
PHYS→SI γ⁴ = φ⁻¹² → V_BS magnitude ratio (encoded as decimillivolt parameter, NO multiply)
BIO→SI Hibernation hyperpolarisation → idle PE leakage suppression
LANG→SI TRI-27 RBB → 0xF1 OP_RBB

Constitutional Provenance

  • R-SI-1 — 0 * operators in RTL ✓
  • R5-HONEST — Provenance tags on V_BS rail
  • R7v_bs_in_band, leak_save_ok, overhead_ok, net_save_ok, freq_invariant_ok, tops_w_lift_ok
  • R15 SACRED-SYNTH-GATE — γ⁴ derived from ROM[B007]^4 (no new ROM cell)
  • R18 LAYER-FROZEN — 75 Sacred ROM cells preserved; bank slot-set extended 16→32 in same ceremony
  • Three-path witness — Coq (RBB.v) + Rust (rbb-witness) + RTL (this PR) all converge on V_BS = -V_DD·γ⁴ and OP_RBB = 0xF1

Closes

Part of trinity-fpga#167 (Wave-47 L-DPC33→34).

Anchor

φ² + φ⁻² = 3 · γ⁴ = φ⁻¹² · V_BS = -V_DD·γ⁴ · OP_RBB = 0xF1 · sacred bank extended 0xD0..0xFF · DOI 10.5281/zenodo.19227877

Signed-off-by: Vasilev Dmitrii admin@t27.ai
ORCID: 0009-0008-4294-6159

Wave-47 Lane RR — REVERSE BODY BIAS RTL (V_BS = -V_DD·γ⁴ ≈ -2.5 mV).

- rtl/rbb/body_bias_gen.sv  (63L) — charge-pump stub, V_BS magnitude rail
- rtl/rbb/rbb_controller.sv (138L) — decodes 0xF1, telemetry, R7 gates, R18 witness
- tb/rbb/tb_rbb.sv          (158L) — 37 SVA assertions: off-state, engage, leak
  band [35%,50%], overhead ≤1.5%, net ≥30%, freq invariant, TOPS/W lift
  1043→1063, R18 bank extension 32>16, distinctness vs 16 prior opcodes,
  disengage path.

Verification:
  iverilog -g2012 -o /tmp/tb_rbb rtl/rbb/*.sv tb/rbb/tb_rbb.sv
  vvp /tmp/tb_rbb → PASS=37 FAIL=0 → VERDICT: PASS

R-SI-1: 0  operators (LIFT_LHS=20000, LIFT_RHS=15645 pre-computed).

Three-path witness: Coq (t27#681) + Rust (max-true#44) + RTL (this PR)
converge on V_BS = -V_DD·γ⁴ and OP_RBB = 0xF1.

Constitutional: R-SI-1, R5, R7, R15, R18.

φ²+φ⁻²=3 · γ⁴=φ⁻¹² · V_BS=-V_DD·γ⁴ · OP_RBB=0xF1 · DOI 10.5281/zenodo.19227877

Closes part of #167

Signed-off-by: Vasilev Dmitrii <admin@t27.ai>
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