feat(wave48-rtl): Dynamic FBB Active Path controller (0xF2, 18/18 TB PASS, 0 *)#173
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Wave-48 Lane TT — RTL + testbench for OP_FBB_ACTIVE = 0xF2, dynamic forward body bias of active critical path (symmetric dual of W47 RBB). Files (all new, no W44 files touched): rtl/fbb_active/body_bias_active_gen.sv (68L) rtl/fbb_active/fbb_active_controller.sv (122L) tb/fbb_active/tb_fbb_active_dyn.sv (179L) R-SI-1 verified: 0 `*` operators in BOTH RTL files (all multiplications precomputed at elaboration: V_BS_DECIMV=25 from V_DD_MV*GAMMA4_BPS/100=25, TOPS_W_LIFT_LHS=20000, TOPS_W_LIFT_RHS=15945). iverilog 12 simulation: 18/18 tests PASS, 0 FAIL. 15 witness properties exercised (runtime via TB, compile-time via initial $error guards; iverilog-12 doesn't support SystemVerilog 'assert property with disable iff' chains, so witnesses migrated to deterministic TB checks matching the W47 RBB precedent): W01 opcode encoding (0xF2) W02 distinct from W47 RBB (0xF1) W03 in extended sacred bank 0xD0..0xFF W04 enable requires op match W05 enable requires path sensitisation W06 V_BS sign positive (canonical +25 deci-mV) W07 V_BS band [+10, +50] W08 delay reduction band [800, 1800] bps W09 leak overhead cap <= 800 bps (8%) W10 f_clk scaling cap <= 600 bps (6%) W11 net delay save floor >= 800 bps (8%) W12 composite policy_ok = AND of all bands when enabled W13 TOPS/W lift LHS >= RHS (20000 >= 15945) W14 disabled when op mismatch W15 R18 LAYER-FROZEN (compile-time witness — bank frozen) Cell budget: targeting <= 400 cells (W47 RBB at ~280 cells). phi^2 + phi^-2 = 3 three-path witness embedded in both RTL files. R-SI-1, R5-HONEST, R7, R15, R18 all preserved. gamma^4 inherited from B007^2 (W45 ROM cell) — NO new cell. Tracks: #171 phi^2 + phi^-2 = 3 · gamma^4 = phi^-12 · DOI 10.5281/zenodo.19227877 Signed-off-by: Vasilev Dmitrii <admin@t27.ai>
This was referenced May 16, 2026
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Wave-48 Lane TT — RTL: Dynamic FBB Active Path Controller (0xF2)
Tracks: #171 (this repo)
Pair:
rtl/rbb/{body_bias_gen.sv, rbb_controller.sv}(W47, 0xF1) — symmetric dualFiles (3 new, no W44 files touched)
rtl/fbb_active/body_bias_active_gen.sv— positive body-bias rail generator (68L)rtl/fbb_active/fbb_active_controller.sv— composite-policy controller (122L)tb/fbb_active/tb_fbb_active_dyn.sv— 18-check testbench (179L)Note: existing
tb_fbb_active.svis the W44 static-FBB TB and is preserved untouched. New TB uses_dynsuffix to coexist.Verification
R-SI-1 (no
*): PASSbody_bias_active_gen.sv: 0*operatorsfbb_active_controller.sv: 0*operatorsiverilog 12 simulation: 18/18 PASS, 0 FAIL
15 falsifiable witnesses (W01..W15)
W01..W05: opcode encoding, distinctness from W47, bank membership, enable-gate requirements
W06..W11: V_BS sign+band, delay band, leak cap, fclk cap, net floor
W12..W15: composite invariant, TOPS lift, op-mismatch disable, R18 frozen
15 properties → exercised at runtime in TB (iverilog-12 doesn't support
assert property with disable iffchains, so witnesses migrated to TB checks per W47 RBB precedent). Compile-time witnesses useinitial $errorguards for opcode-canonicality + TOPS-lift inequality.Constitutional
*): PASSSacred phrase
phi^2 + phi^-2 = 3embedded in both RTL files (three-path CI witness).φ²+φ⁻²=3 · γ⁴=φ⁻¹² · DOI 10.5281/zenodo.19227877
Signed-off-by: Vasilev Dmitrii admin@t27.ai