🔴 [WAVE-24 W15-TT-E] fix(info.yaml): wire MAX top_module → tt_um_trinity_max · 4x4 tile size#44
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🔴 [WAVE-24 W15-TT-E] fix(info.yaml): wire MAX top_module → tt_um_trinity_max · 4x4 tile size#44gHashTag wants to merge 1 commit into
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…ent) PR #39 added MAX RTL but info.yaml still pointed at Mid top — GDS was building Mid, not MAX. This flips the YAML to submit MAX 4×4 mesh. R-SI-1 status: legacy gf16_mul.v `*` is grandfathered (TRI_NET_SHUTTLE_TRIAD Rule 2, Issue #4 deferred-ttsky26c label). No RTL changes needed for W15-TT-E. EPIC: gHashTag/trinity-fpga#61 · phi^2+phi^-2=3
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🔴 MAX GDS Enablement — info.yaml wire-up (W15-TT-E)
Change Summary
Single-file change: only. Zero RTL modifications.
New source_files prepended:
1.
2.
3.
All existing Mid source files kept — instantiates which depends on , , etc.
Problem Fixed
PR #39 (, HEAD ) added the MAX RTL (, , + testbench) but still pointed at Mid top-module . The GDS workflow was building Mid, not MAX. This is a true blocker: MAX silicon exists in the repo but was not being submitted.
R-SI-1 Status — NO ACTION REQUIRED
Rule R-SI-1 = "no NEW operators in synthesisable RTL".
→ 69 cells are legitimate. No Wallace-tree replacement needed for this wave. Replacement is deferred to ttsky26c per Issue #4.
GO Call
This PR enables MAX GDS submission for W15-TT-E. No RTL was modified. The only change is pointing the toolchain at the correct top-module and tile footprint.
Status: GO — unblocks W15-TT-E MAX physical implementation.
Author: Vasilev Dmitrii admin@t27.ai
EPIC: gHashTag/trinity-fpga#61
Anchor: phi^2 + phi^-2 = 3