fix: Lane L clock relax 40MHz + resizer margins — Plan B

[gHashTag]

Plan B: Fast-Path Clock Relaxation for Lane L GDS

This PR is the fast-path fallback for TT submission if the structural fanout-splitting fix (PR #46 sibling) does not land in time for the Tiny Tapeout submit window (deadline 2026-05-18 22:00 UTC).

Changes

Parameter	Before	After
CLOCK_PERIOD	20 ns (50 MHz)	25 ns (40 MHz)
GRT_RESIZER_SETUP_SLACK_MARGIN	(unset)	0.3 ns
PL_RESIZER_SETUP_SLACK_MARGIN	(unset)	0.3 ns
PL_TARGET_DENSITY_PCT	45%	40%

Rationale

PR #46 attempts a structural fanout-split to make the design close at 50 MHz. That is the preferred path. However, if the OpenLane flow does not converge with positive setup slack in time, this PR provides a working GDS by:

1. Relaxing the clock from 20 ns → 25 ns, giving the critical paths 5 ns of additional budget (sufficient to absorb the Lane L fanout violation without structural changes).
2. Tightening resizer setup margins (0.3 ns for both placement and global-route resizers) so that buffers are inserted more aggressively, reducing transition-time degradation on high-fanout nets.
3. Lowering placement density from 45% → 40%, easing the router congestion that contributes to detour-induced hold/setup interaction.

Decision criteria

• If PR feat(v2.1): Lane L OpenROAD CGT clock-gating — +12% dynamic, unlocks v2.1 75 TOPS/W #46 (fanout-split) achieves WNS ≥ 0 at 50 MHz before 2026-05-18 20:00 UTC → merge PR feat(v2.1): Lane L OpenROAD CGT clock-gating — +12% dynamic, unlocks v2.1 75 TOPS/W #46, close this PR.
• If PR feat(v2.1): Lane L OpenROAD CGT clock-gating — +12% dynamic, unlocks v2.1 75 TOPS/W #46 is still failing or untested at that point → merge this PR as the safe fallback.

Anchor

φ² + φ⁻² = 3