Fix Phase-B capability contract

[Th0rgal]

Summary

Narrow the Phase-B advertised device capability to INTERPRETER_COMPAT (0x00000002), matching packet RTL behavior. Add mutation-sensitive coverage for valid negotiation, supported interpreter-compatible operation, and rejection of unadvertised FORWARD_ONLY.

Validation receipts

• PASS — official BLAKE3 differential: exit 0, 1426 ms
• PASS — repository Python suite: exit 0, 11544 ms (288 tests)
• PASS — model/RTL differential: exit 0, 1110 ms
• PASS — bounded RTL simulation: exit 0, 129 ms
• PASS — mutation regression: exit 0, 400 ms
• PASS — RTL-to-netlist synthesis (timeout 900s): exit 0, 447965 ms

The full commands, logs, hashes, and receipts are committed in results/b2-capability-contract-20260728/README.md.

Explicit release boundary

Sequential equivalence is not established. The lowered RTL/netlist attempt stopped with 5,039 unproven $equiv cells (exit 143 after 585606 ms). The repository lacks the required flattening/state-correspondence release harness and reset assumptions for the receiver, transmitter, adapter, and field-encoder submodules.

This PR is not ASIC-readiness evidence and must not be merged without a new owner instruction.

[Th0rgal]

Exact-head independent review of dab8b083b210ecbb04e5ff49c649949a40a56eb6 (tree 01b8e6c27818b491dddf78ca5d0b0816ac69ba3f): no technical findings.

I independently reran the RX reset proof, concrete STATUS-accept proof, stalled INFO-response serializer proof, full milestone runner, and bounded serializer mutation target from source. All exited 0; the SAT proofs reported success, and the deliberate status-serialization mutation was rejected by a failed assertion. The RX/TX timelines are reachable under satisfiable assumptions, and the TX completion timing requires both fixed ready-low cycles. Changed-source forbidden-token scan, receipt checksums, repository consistency, and claim-boundary audit are clean. GitHub currently reports zero review threads.

The bounded wording is accurate: this is not an arbitrary-backpressure, monolithic controller end-to-end, release-equivalence, or ASIC-readiness proof.