Fix Phase-B capability contract

asic_core/rtl/gf128_mul_bitstream.sv

@@ -20,7 +20,9 @@ module gf128_mul_bitstream (
     input  wire         bit_last,
 
     input  wire         result_shift,
-    output wire [7:0]   result_byte
+    output wire [7:0]   result_byte,
+    output wire [127:0] arch_a_shift,
+    output wire [127:0] arch_accumulator
 );
 
     gf2n_mul_bitstream #(
@@ -38,7 +40,9 @@ module gf128_mul_bitstream (
         .bit_value    (bit_value),
         .bit_last     (bit_last),
         .result_shift (result_shift),
-        .result_byte  (result_byte)
+        .result_byte  (result_byte),
+        .arch_a_shift (arch_a_shift),
+        .arch_accumulator (arch_accumulator)
     );
 
 endmodule

asic_core/rtl/gf2n_mul_bitstream.sv

@@ -37,7 +37,9 @@ module gf2n_mul_bitstream #(
     input  wire                    bit_last,
 
     input  wire                    result_shift,
-    output wire [BYTE_BITS-1:0]    result_byte
+    output wire [BYTE_BITS-1:0]    result_byte,
+    output wire [WIDTH-1:0]        arch_a_shift,
+    output wire [WIDTH-1:0]        arch_accumulator
 );
 
     reg [WIDTH-1:0] a_shift;
@@ -68,6 +70,8 @@ module gf2n_mul_bitstream #(
     endfunction
 
     assign result_byte = accumulator[BYTE_BITS-1:0];
+    assign arch_a_shift = a_shift;
+    assign arch_accumulator = accumulator;
 
     always @(posedge clk) begin
         if (!rst_n) begin

asic_core/rtl/leanvm_b_stream_alu.sv

@@ -40,7 +40,12 @@ module leanvm_b_stream_alu (
 
     output wire       busy,
     output wire       done_pulse,
-    output reg        fault
+    output reg        fault,
+    output wire [3:0] arch_state,
+    output wire [3:0] arch_byte_index,
+    output wire [7:0] arch_scratch_byte,
+    output wire [127:0] arch_mul_a_shift,
+    output wire [127:0] arch_mul_accumulator
 );
 
     localparam [7:0] CMD_XOR128  = 8'h01;
@@ -97,10 +102,15 @@ module leanvm_b_stream_alu (
         .bit_value    (mul_bit_value),
         .bit_last     (mul_bit_last),
         .result_shift (mul_result_shift),
-        .result_byte  (mul_result_byte)
+        .result_byte  (mul_result_byte),
+        .arch_a_shift (arch_mul_a_shift),
+        .arch_accumulator (arch_mul_accumulator)
     );
 
     assign busy = (state != S_IDLE);
+    assign arch_state = state;
+    assign arch_byte_index = byte_index;
+    assign arch_scratch_byte = scratch_byte;
 
     function automatic [7:0] status_byte;
         input [3:0] index;

asic_core/rtl/lsc1_field_encoder.sv

@@ -12,7 +12,31 @@ module lsc1_field_encoder (
     output reg          busy,
     output reg          done_pulse,
     output reg          fault,
-    output reg  [127:0] result
+    output reg  [127:0] result,
+    output wire [4:0]   arch_bit_index,
+    output wire [15:0]  arch_saved_index,
+    output wire         arch_multiply_start,
+    output wire [127:0] arch_accumulator,
+    output wire [127:0] arch_operand_a,
+    output wire [127:0] arch_operand_b,
+    output wire         arch_done_pulse,
+    output wire         arch_fault,
+    output wire [127:0] arch_result,
+    output wire [2:0]   arch_multiplier_state,
+    output wire [7:0]   arch_multiplier_operation,
+    output wire [5:0]   arch_multiplier_payload_index,
+    output wire [4:0]   arch_multiplier_result_index,
+    output wire [127:0] arch_multiplier_saved_a,
+    output wire [127:0] arch_multiplier_saved_b,
+    output wire         arch_multiplier_done_pulse,
+    output wire         arch_multiplier_fault,
+    output wire [127:0] arch_multiplier_result,
+    output wire [3:0]   arch_multiplier_core_state,
+    output wire [3:0]   arch_multiplier_core_byte_index,
+    output wire [7:0]   arch_multiplier_core_scratch_byte,
+    output wire         arch_multiplier_core_fault,
+    output wire [127:0] arch_multiplier_core_mul_a_shift,
+    output wire [127:0] arch_multiplier_core_mul_accumulator
 );
     reg         multiply_start;
     reg [4:0]   bit_index;
@@ -22,6 +46,15 @@ module lsc1_field_encoder (
     wire        multiply_busy, multiply_done, multiply_fault;
     wire [127:0] multiply_result;
     reg [127:0] next_accumulator;
+    assign arch_bit_index = bit_index;
+    assign arch_saved_index = saved_index;
+    assign arch_multiply_start = multiply_start;
+    assign arch_accumulator = accumulator;
+    assign arch_operand_a = operand_a;
+    assign arch_operand_b = operand_b;
+    assign arch_done_pulse = done_pulse;
+    assign arch_fault = fault;
+    assign arch_result = result;
 
     function automatic [127:0] field_xtime(input [127:0] value);
         field_xtime = {value[126:0], 1'b0} ^
@@ -32,7 +65,16 @@ module lsc1_field_encoder (
         .clk(clk), .rst_n(rst_n), .abort(abort), .start(multiply_start),
         .operation(8'h02), .operand_a(operand_a), .operand_b(operand_b),
         .busy(multiply_busy), .done_pulse(multiply_done),
-        .fault(multiply_fault), .result(multiply_result)
+        .fault(multiply_fault), .result(multiply_result),
+        .arch_state(arch_multiplier_state), .arch_operation(arch_multiplier_operation),
+        .arch_payload_index(arch_multiplier_payload_index), .arch_result_index(arch_multiplier_result_index),
+        .arch_saved_a(arch_multiplier_saved_a), .arch_saved_b(arch_multiplier_saved_b),
+        .arch_done_pulse(arch_multiplier_done_pulse), .arch_fault(arch_multiplier_fault),
+        .arch_result(arch_multiplier_result),
+        .arch_core_state(arch_multiplier_core_state), .arch_core_byte_index(arch_multiplier_core_byte_index),
+        .arch_core_scratch_byte(arch_multiplier_core_scratch_byte), .arch_core_fault(arch_multiplier_core_fault),
+        .arch_core_mul_a_shift(arch_multiplier_core_mul_a_shift),
+        .arch_core_mul_accumulator(arch_multiplier_core_mul_accumulator)
     );
 
     always @(posedge clk) begin