Add LSC-1 Tiny Tapeout ttsky26c integration lane

[Th0rgal]

Summary

• add a uniquely named tt_um_* ttsky26c wrapper around the unchanged asic_core/ LSC-1 boundary
• explicitly map the 8-bit request/response ready-valid lane and safely clamp/disable every output while ena is low
• add honest yaml_version 6 metadata, a conservative but unproven 2x2 candidate, LibreLane config, cocotb RTL/GL tests, and ttsky26c GDS/precheck/gl_test/viewer workflows
• document source boundaries, pin ownership, local evidence, and unresolved physical-design claims

Immutable base

• commit: fda85f5efc6f5b460d72204b4d9c0d882960ec29
• tree: df42a6211828d856e9a21ba61ecc2cd1b9dc4e71
• asic_core/ diff from base: empty

Local PASS evidence

• Icarus SystemVerilog elaboration: exit 0
• Yosys hierarchy/proc/check: exit 0
• make -C test cocotb Tiny Tapeout lane test: exit 0
• make check: exit 0
• make sim: exit 0
• tt_tool.py --create-user-config: exit 0
• make checksum-check: exit 0

Unresolved / authoritative CI

• local make lean: exit 2; real Lake binary unavailable
• local make formal: exit 2; sby unavailable
• local tt_tool.py --harden: exit 1 before physical design; LibreLane module unavailable and PDK_ROOT unset
• GDS, precheck, DRC/LVS, gate-level simulation, timing, area/tile fit, and PPA are not claimed
• the real TinyTapeout/tt-gds-action@ttsky26c jobs on this draft PR are the authoritative external attempt

This PR does not claim ASIC readiness and must not be merged based only on RTL results.