Add LSC-1 Tiny Tapeout ttsky26c integration lane

.github/workflows/ci.yml

@@ -77,6 +77,8 @@ jobs:
           select -assert-min 4 leanvm_b_mul_pulse_check*/t:$check'
       - name: Multiplier pulse mutual-exclusion proof on shipped RTL
         run: cd formal && sby -f stream_alu_mul_pulse.sby
+      - name: LSC-1u protocol and retained-boundary proofs
+        run: cd formal && sby -f lsc1u_protocol.sby
       - name: Yosys lint and synthesis
         run: >-
           yosys -p 'read_verilog -sv asic_core/rtl/gf2n_mul_bitstream.sv asic_core/rtl/gf128_mul_bitstream.sv asic_core/rtl/leanvm_b_stream_alu.sv

.github/workflows/gds.yaml

@@ -0,0 +1,45 @@
+name: gds
+
+on:
+  push:
+  workflow_dispatch:
+
+jobs:
+  gds:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: checkout repo
+        uses: actions/checkout@v6
+        with:
+          submodules: recursive
+      - name: Build GDS
+        uses: TinyTapeout/tt-gds-action@30d38a7dfc6fda561d452b196fc822af0332ec23 # ttsky26c
+        with:
+          pdk: sky130A
+
+  precheck:
+    needs: gds
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Run Tiny Tapeout Precheck
+        uses: TinyTapeout/tt-gds-action/precheck@30d38a7dfc6fda561d452b196fc822af0332ec23 # ttsky26c
+
+  gl_test:
+    needs: gds
+    runs-on: ubuntu-24.04
+    steps:
+      - name: checkout repo
+        uses: actions/checkout@v6
+        with:
+          submodules: recursive
+      - name: GL test
+        uses: TinyTapeout/tt-gds-action/gl_test@30d38a7dfc6fda561d452b196fc822af0332ec23 # ttsky26c
+
+  viewer:
+    needs: gds
+    runs-on: ubuntu-24.04
+    permissions:
+      pages: write
+      id-token: write
+    steps:
+      - uses: TinyTapeout/tt-gds-action/viewer@30d38a7dfc6fda561d452b196fc822af0332ec23 # ttsky26c

.github/workflows/tt-test.yaml

@@ -0,0 +1,20 @@
+name: Tiny Tapeout RTL test
+on: [push, workflow_dispatch]
+
+jobs:
+  test:
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Checkout repo
+        uses: actions/checkout@v6
+      - name: Install iverilog
+        run: sudo apt-get update && sudo apt-get install -y iverilog
+      - name: Setup Python
+        uses: actions/setup-python@v6
+        with:
+          python-version: "3.11"
+      - name: Install test dependencies
+        run: pip install -r test/requirements.txt
+      - name: Run Tiny Tapeout RTL test
+        working-directory: test
+        run: make

.gitignore

@@ -19,6 +19,11 @@ formal/gf128_serialize_cover/
 formal/stream_alu_mul_pulse/
 formal/stream_alu_mul_pulse_induction/
 formal/stream_alu_mul_pulse_cover/
+formal/lsc1u_protocol_bmc/
+formal/lsc1u_protocol_cover/
+test/results.xml
+test/sim_build/
+.venv/
 openlane/
 reports/
 tools/blake3_reference/target/

Makefile

@@ -80,6 +80,7 @@ lean:
 
 formal:
 	cd formal && sby -f gf8_mul.sby
+	cd formal && sby -f lsc1u_protocol.sby
 
 clean:
 	$(MAKE) -C test clean

README.md

@@ -28,6 +28,13 @@ the [proof-boundary matrix](docs/PROOF_BOUNDARIES.md),
 Frozen leanVM-b evidence remains tied to
 `c308034ab78619b39a59d26f3dc60e7df5b52649` and is never relabeled.
 
+> [!IMPORTANT]
+> **LSC-1µ (LSC-1 Micro) is the deliberately reduced Tiny Tapeout
+> profile/sub-core of LSC-1. It is not “LSC-1/2”, LSC-2, or a second-generation
+> architecture.** ASCII identifiers use `LSC-1u` / `lsc1u`. Full LSC-1 remains
+> unchanged for FPGA and future larger ASIC targets. See the
+> [LSC-1µ architecture contract](docs/LSC1U_ARCHITECTURE.md).
+
 ## Layout
 
 - `asic_core/`: exact Tiny Tapeout LSC-1 RTL boundary.
@@ -41,6 +48,7 @@ Frozen leanVM-b evidence remains tied to
   frozen-upstream Rust differential adapter.
 - `planning/`: machine-readable milestones and file-lane ownership.
 - `src/`: retained compatibility/historical MinCore and M2 sources.
+- `src/lsc1u_core.sv`: profile-specific streamed LSC-1µ arithmetic kernel.
 
 Run `make check`, `make sim`, `make lean`, and `make formal` where the
 corresponding tools are installed. `make consistency` rejects stale active

SHA256SUMS

@@ -1,9 +1,11 @@
-3ab4c0298695ac927493f923d3d42015a0d413900c2b0102d10d42fc85ecf766  ./.github/workflows/ci.yml
-53c8efe9491c0fb3fde6db8e79d7fed66b8d9593d92db360fb95d2adb2ed56a4  ./.gitignore
+4ab8771d2a24fc127b404e8024e61544f3ca409ee0dc58b349eadcd457484511  ./.github/workflows/ci.yml
+5e6a29a5b46af46a1d8ebb9cb9ed4b4042d492b86c752e7aaa845dc73c164c2f  ./.github/workflows/gds.yaml
+dc4fd27671dc6184c8106cac4193bada03706186206784f4cd872ca183592494  ./.github/workflows/tt-test.yaml
+160fb469e2232fac0b9e620106c3ca72c8fadbb34f75892f5186bc3b5a798883  ./.gitignore
 cfc7749b96f63bd31c3c42b5c471bf756814053e847c10f3eb003417bc523d30  ./LICENSE
 6bdbfe37959e0283134042372101a8a446432eb2516e085bf7850a712720c3c5  ./MANIFEST.md
-46eac72b525297a0c233bc624faa6cbcbf5e5cf106520854a765e151b6c9822a  ./Makefile
-5ad7fec74f48ad429f8f66411a292f75f8be9e80760071c6069d5534c43aae83  ./README.md
+146b21b4eb36549844359d9910ce49200ee980fd98f925be07ee27bc8672b65a  ./Makefile
+30fdeb94f91b6b8b57a05ffec53239284ec23366508bd0a5d59430cdde824d4d  ./README.md
 de4c0f6adf6ff1356bf9d7599ab52aef93a00b50c5a77c727ec0ce036ff2d1a2  ./RESULTS.md
 baa38ad5792511470f4cc9d2344d46f0c7af8a365d5b5e178dca88634b288bff  ./VALIDATION.txt
 56f3315873ddf849b851b0fb106e9eeec7160c33d15914c6157d7fe13065b6b5  ./VERSION
@@ -29,6 +31,7 @@ ac44a1838e7da255ed93835cc0de01e1751efc05f78cf9f8b8145cc963d6836a  ./docs/DECISIO
 5ecf1ccdc8eb9562aaee69502fab30727351290892df2483e29680149eada14f  ./docs/FULL_CORE.md
 b989d03d5e6c7dd3c1c11bf40277da8d700463601f23c8c51787f8ac371bc596  ./docs/FULL_CORE_PROTOCOL.md
 42e5b0f0b0f98d2c7c89cbc5db737b1d1f2dd02685f4f07b98ea709a7f9e7690  ./docs/HOST_RUNTIME.md
+fdebab4c908e5b84d41cd83cb880e23fa68cbf14f556115f0ba19b0bad377934  ./docs/LSC1U_ARCHITECTURE.md
 59832e723e7c3e52b1e23ce70fb30760b6221b5e135c54ee5556775b7cf792f3  ./docs/LSC1_PROTOCOL.md
 549ecdb6797df667096e3081f26357ff3aa33de323b65aae7445f77902d017a9  ./docs/LSC1_TRANSACTION_PROTOCOL.md
 c41da7c4e22cc809e471da2bfcce176505db234c3b48e9c01ff20b8bcaef4b29  ./docs/M0_MANAGER.md
@@ -43,8 +46,9 @@ b81b89574ed84c67b64ae7b56001bf9d03b9d66be2bed7977d8adc715481eafb  ./docs/PROTOCO
 6ec7c4c80628391da706725be1a2361ae8eb2ee014fb4cde6dae31c53f13e9f0  ./docs/SEMANTIC_DIFFERENCES.md
 02e8a5b52b341390f008ff8bc62f5d2d982b23adb8b26cb73ef3b07dddeed807  ./docs/SOURCE_AUDIT.md
 63a4e673f49e169d587cb2302547cc251add4531c62908a38dadc169eaa312d3  ./docs/STATUS.md
-9c2582c40fbd9a4e2b163abed784f5a6c82b2cb3136c37a4123a0ba6584f6136  ./docs/TAPEOUT.md
+12d791e2dfa543d0b2295fd2c0c388596c1a5b8f2dcbe649ba33abedcc19d82e  ./docs/TAPEOUT.md
 0d976224f3f8c1198e8f0c51c0f4d022bd7c6f3dfcd36653f6d82bdfe2ae36c4  ./docs/THEOREM_INVENTORY.md
+67a886e53f467b63e24b850ea3ebf4f6548dd9bdf76102fb57ad2002eaf9273c  ./docs/TINY_TAPEOUT_TTSKY26C.md
 e61e74c84bce2ec92ef18520eb134299f9341e63d3ec43cdbe0ef4879d22ba37  ./docs/ULX3S_SMOKE_AND_UART.md
 a08743f1a3cf4af68683cdaac5b00ca624ac875dbeef9f78614bda7297579df8  ./docs/USE_CASES.md
 20aa56b3f69c28c9639e9bd16b8239f0ef511d8fded9340185814b3257e25f01  ./docs/VALIDATION.md
@@ -61,6 +65,8 @@ d99deb35f0ccb83779670acf8dcdece29cfa502dda4bed6d86cc84dc8f5fb836  ./formal/gf128
 15abdc4c23f94b7389e25487e4c4d35a13ed1565882cbe449629bcbc6a488419  ./formal/gf8_mul_bounded_boolector.sby
 531723ced686badb599022ea068d4b94f1d7e00f83ed3d7b86a9f91cc59448f2  ./formal/gf8_mul_depth22_z3.sby
 25a0d4fe96e4bcd910ebac0ba76be01f8924aedfa1f7e83588610f1a758baf4f  ./formal/gf8_mul_formal.sv
+bd50a291e3d633181f4383f8f7dd631f0d1deb37314cd29766692753e91a9363  ./formal/lsc1u_protocol.sby
+bec30f66a42335415108a517015080520e84cf21b11bf3c4fb7353b407850108  ./formal/lsc1u_protocol_formal.sv
 1e6b80dd959472d00411116899097fb37c930651efe6290fda93a8f4ae5ae97e  ./formal/stream_alu_mul_pulse.sby
 b61a1ea32d6b114093dd2679fd4fb3315dbfbb9829b8e4f739c0177f66ff1bc1  ./formal/stream_alu_mul_pulse_formal.sv
 53da30df5dd375567994d2e071664456f0c90d420710817fbbb4b53d894b668a  ./fpga/ulx3s/Makefile
@@ -81,7 +87,7 @@ dad7d78465d3b8f339d22d79c0823e52dc587fba26272b4f6fd7ce6ed1de6201  ./fpga_harness
 5afe24acc0e398a66591f66ef62fb63ca300c2f925f9de828547e7e9ea8b302e  ./fpga_harness/INVENTORY.md
 17cbb54c9085c6dde96caf6bf8294444339d6878d65d9aa1f5cb193705e5f2e3  ./fpga_harness/README.md
 a538a3b5e64df095b867eb23f77953be4ea021a5d755f45f13a7b9a8ed8e7ccb  ./fpga_harness/board_detect.py
-f00b4c8c96b74b20c75ebc0cd3cc042def53f39d9cf1d963435e9b2e8f96e176  ./fpga_harness/boundary_check.py
+00fa44f3e6a43bc6e833031b50dcc5f228472d6ad336951448bcd8b4a924a61f  ./fpga_harness/boundary_check.py
 ac042826f976c6e04c668613676b006743f487a463e2cd6a2ca14a5f31571502  ./fpga_harness/fixtures/ulx3s_full_visibility.json
 15eafd1c269122e92939f4bded3c778b802e15c01d26001cc20a09b6d2a0fbe0  ./fpga_harness/hardware_preflight.py
 7571676d26daf04b94b9fadbdbc9740568ea92439ae0830f41a7567fdbd002a7  ./fpga_harness/host/__init__.py
@@ -110,7 +116,7 @@ c22e2dd6edcd014dd803fd1ea630ae063aeee86e192afd6c34b4ac81efa73daa  ./host/lean_co
 809335481a0314cc5231d26931bfdef14343cdae5fdf6025576ea1ab17dcac89  ./host/memory.py
 451f3d686ce47b16d81de2f85d36a52231c99a1b47c261475c0cb4134a09d777  ./host/protocol.py
 f3b64010406928c48e879ad0ec9a539acec43971570a8a5b4ee25024a4b52502  ./host/runtime.py
-effcad52a728f7c1cc4b463ea8d7bc6cc6350ddb6daf836f4adc601f714485ab  ./info.yaml
+f1194bbf4d72e9f2a1a0c4dffb6d0137fbd6eca56fb1cd22246ab6c74546336e  ./info.yaml
 68a4209dcbdcc663454d02012642fa7b5a3476a13e363982fc9236e89c27a6b7  ./lean/LeanVMBMinCore.lean
 c09c6cf1a82598ec2c0e5f6ecf58852c8c27554f7036f36baadf027067a55f4e  ./lean/LeanVMBMinCore/Address.lean
 70ce5c26e2964f9c095505c2a621e5bdc08a9379656048ef5cc6d350d9a0bf31  ./lean/LeanVMBMinCore/ByteSerialization.lean
@@ -308,6 +314,7 @@ e3329b92c1baf92fa161eb36a067e2ccbe73342fe8e419c315fbadfef9729b7d  ./results/ulx3
 2ce193a38f1a8c96ec1cbfe2c8b7555d025944cb450859c3e09dd2cbab66a03c  ./sim/__init__.py
 56f95ab49ce35604c5b30cd95d142a4d630b2d503af5398b1f975ef84492b48c  ./sim/cycle_model.py
 3ebec652b76c20903fde598d748dbaff596cbc3f962f80ca23f30b31e1327da5  ./sim/lsc1_transaction.py
+c9ab7832b0691e2221ad73dc40a581023c28cd6e7fbfe2406ae491c77cfafd0c  ./sim/lsc1u_model.py
 12dd1aca968efeafb9ffa7015f849607c96fb6e14ad2aa8f65938dd254ef6f49  ./sim/model.py
 dee5dc820b96f24d4dbd752b17aaad3c8e025d519c043dfd1ab7c46be5600245  ./sim/packet_executor_model.py
 659496fd9f21edafb7c4c12500d9b623bd0ea063808dc9494053ad923102dc31  ./sim/protocol_contract.py
@@ -319,25 +326,34 @@ a2fda9c21da5f3301de411060ffbb644c08c4c5e4c103e036b3834e2922ce10a  ./sim/test_cyc
 002325ca4bcceb7b5ec19e8b279df399661ac368b118eb160d97a6a450fe74e7  ./sim/test_host_runtime.py
 f1ab500117ae9d7a20a9258a32dbc7271b4d0ec5f57d3fc058ff426ba2289a40  ./sim/test_lsc1_protocol_doc.py
 2c19d774213f293a361de949f7cecc99b35111cc9afe5da73bac924d02b2747d  ./sim/test_lsc1_transaction.py
+eeb0ad5bc4246bc3d1163393c6224bc0c045812157742031d173124d7d429299  ./sim/test_lsc1u_model.py
 3e8c789984dbc6b6150881f9aa823aaaef80e4e8b90eb329e9e9e351bfbe9b06  ./sim/test_model.py
 b6f8a2af3bdba662f41be970f3a43ed6e5a9f4ec0cb69a11b2087b2acfa8b691  ./sim/test_packet_executor_model.py
 cfad76ffba1453cc8c7f76dd688d55201aa4f9b83fbd726ab77b72d201e0a62a  ./sim/test_packet_frontend_rtl_differential.py
 c128acb44fa334177d240255f997d4e245d6a996db5938d65deca48962ebce79  ./sim/test_protocol_contract.py
 8486656729b8978f8059189845dff97dad929befde94cb3cb89ad9febf08753b  ./sim/test_scalar_step_oracle.py
+40ea3446c5885880a4da0a59b1a2553188f2e8613f2008f843abd5273f86f544  ./src/config.json
 d8e83531981677f629877cbeff643e07e169f8f6e8cf3ecd7c1b0c417a79b614  ./src/gf128_mul_bitstream.sv
 4aa363edd4a6b2797191599d838f3d5f81cc97aa5fc8d88f2f0050420ccf6396  ./src/gf2n_mul_bitstream.sv
 f3e038032b2f1c76b176651dd79b266976091f1215b7e617c194888e387ab5e5  ./src/leanvm_b_m2_scalar_controller.sv
 bf844b461def08fbf5b69093f95f792fd9302b26098351d192e32c76583f001b  ./src/leanvm_b_stream_alu.sv
+0fb39cd775beb6a76dd4ad30728937f6eabe35ee951e939f51d8d80456793087  ./src/lsc1u_core.sv
 e97452e6444238c80a86811f86d892a0db6e79e498d00afc638387f8656ef28c  ./src/tt_um_leanvm_b_mincore.sv
-a3574d9d454d7b7580d2dcdc2801013a7648c48358a3f4a90a5c876ae9791331  ./src/user_config.tcl
-69cd41bda612b601228752f516472df0f3be356de2f327ce4bbaaccb588edcf7  ./test/Makefile
+bd60c7c4140ad69af8fa6da8a02e5eb3be7224a6aa2d70d3c6762e3685222102  ./src/tt_um_lfglabs_lean_silicon_lsc1.sv
+595b51e8411023c614163030d621dcb906d9152108874655759d8a9a0e0cdc03  ./src/tt_um_lfglabs_lsc1u.sv
+a9e12c7785940b058ea8976694b79d186a82cf3a111215cd6a4dd259c029c2ec  ./src/user_config.tcl
+56b41ad9df61282e60ec313ba69cd4c89d5bf9f8802a8c7026eca7f748ed2b4e  ./test/Makefile
+258e92c9b01b56b6f1443e18b6b478af5e510ecda337a253155499951712d7af  ./test/Makefile.tt
 89275e550ed74ce4b6fd8dc55c7fbf92b95ff5c26cb4f5a9315e4ac1c20a0192  ./test/packet_frontend/Makefile
 da38796aaa0eb9785e858d9e14bdcf246790410c0b79baa349ff8afa3d14b5f4  ./test/packet_frontend/tb_lsc1_packet_frontend.sv
 f1bf4caf7438081d289ea48ebfcbed8f278866a664636dc810ea5e2c1b4410c3  ./test/packet_frontend/tb_lsc1_packet_vector.sv
+4273151bc1544b57436ccd1af30e6428beb0291e4f9fba3307db8115ef53f60d  ./test/requirements.txt
 d0c03fb87fe5f08fbec435d485e4dd14c96d164e90b0e8b0ed8980cf27e8c077  ./test/tb_m2_scalar_controller.sv
 2ea0bf23432e7c9471b09d7dac47b1b548f37d746a8cdf1fc9bd8128cd2a8018  ./test/tb_packet_uart_bridge.sv
 b78b938f396ae20d1fdccde99281430778a879808e60a35788b6fe044151329c  ./test/tb_stream_alu.sv
 1cdfef46a813dd43f5700b5e3ed7ec0bfb07e07403c82f8ac8fa4fb4dfbd0d55  ./test/tb_uart_bridge.sv
+82e3588552877cf87b22f4eb269e597d75adc0929efd01e221d45375ec28984d  ./test/test_tt.py
+d571f9ffc49ce4232c671d2535fa4862a4800134254230ca29daae74130147a9  ./test/tt_tb.sv
 e401ecd06a20a3f1e54de6e47ff6e12f61064bd2b9278517fe3d0db97933bd8a  ./tools/atomic_publish.py
 7894f75175f62edfd1ed33639a23d736ad6e57ddd9182e040f556502bff21a52  ./tools/blake3_reference/Cargo.lock
 e28e67bc3fd6dee898130648c74691ca7b8e61d1fccfa75c52d87d52fc8d9c3f  ./tools/blake3_reference/Cargo.toml
@@ -351,11 +367,11 @@ a1fbbcbe225a1e2edb2456f92825e7b6853f224e8d0379aa4454d298c2419919  ./tools/frozen
 002cac3d59f29613e237142d4dedc33d25bac1fc11b45bec65a402c528507dc0  ./tools/generate_checksums.py
 0cb6c11945cd152db661b39e7116af8cc53ed4ab02a3cd33b11938069a1ee72a  ./tools/generate_conformance_corpus.py
 35d18cfd8627ecd5441d7084b2c47f332320d96acff285aa557daf53a813647a  ./tools/host_upstream_comparison.py
-0505e646089ff7b98b528140c596a2c93a6a9238013296111f39987def68e1f5  ./tools/interface_consistency.py
+37fc25a825fca61c4a2fe67ed1ccdf3bbd048ed8f02c806efd54319cc96e67b2  ./tools/interface_consistency.py
 87bf0131d197add11cab19ba34e9278a16dddcc066e254ca77b3c28d46b9da4b  ./tools/lean_compiler_export.py
 13cda9f3b47fda14a1ea23b3e210212eacd7250ea15ffd1e1ac638ea0d5bff3a  ./tools/m2_rtl_differential.py
 737518912d916251885645517f2d5cabf3c786b47c71cb9f725cf3ae2c985326  ./tools/portable_build_support.py
-af28d238b411fcc075bb00b09a204ed1a98c4b4c36479ab5aa6ca611928efba0  ./tools/repo_consistency.py
+774f5d1a0041034cf769fcf504d91a316849ea8eb4b7843d6e54f3b830d14658  ./tools/repo_consistency.py
 d39b590b15a494a1e62ff7605ca3b8c8ffec122e0f10f6dce7f997fcecceef1b  ./tools/rtl_state_count.py
 a2b4b3a985df1ecde148745dcc94684c77364cf9a4fa22735f2f4754aa0489db  ./tools/source_provenance.py
 77760424b9ccaea9dfca5b3ac0412cce74db801bf583f4b7d32eb6d9b80b255d  ./tools/sv_smoke_check.py

docs/LSC1U_ARCHITECTURE.md

@@ -0,0 +1,69 @@
+# LSC-1µ (LSC-1 Micro) architecture contract
+
+> **LSC-1µ is a deliberately reduced Tiny Tapeout profile/sub-core of LSC-1.**
+> It is not “LSC-1/2”, not LSC-2, and not a second-generation architecture.
+> Full LSC-1 remains unchanged for FPGA and future larger ASIC targets.
+> ASCII contexts use `LSC-1u` and `lsc1u`.
+
+## Retained semantic boundary
+
+LSC-1µ accepts fixed-width byte-streamed micro-operations:
+
+| Opcode | Operation | Accepted payload | Response |
+| --- | --- | --- | --- |
+| `0x01` | GF(2¹²⁸) XOR | `A0,B0,...,A15,B15` | `A XOR B`, 16 bytes |
+| `0x02` | GF(2¹²⁸) MUL | `A0..A15,B0..B15` | `A × B`, 16 bytes |
+| `0x03` | SET | `V0..V15` | `V`, 16 bytes |
+
+All retained values use the exact LSC-1 convention: byte 0 and bit 0 are
+least-significant; multiplication is in GF(2¹²⁸) modulo
+`x^128 + x^7 + x^2 + x + 1` (low reduction constant `0x87`). SET is an exact
+copy and XOR is bitwise. There is no weakened or alternative arithmetic.
+
+An unsupported opcode produces one `0xe0` response byte and asserts `FAULT`
+until that byte is accepted or a new supported command is accepted.
+
+## Explicit exclusions and host responsibilities
+
+LSC-1µ does **not** implement LSC-1 packet framing, packet CRC, transaction
+orchestration, instruction fetch or memory, DEREF/JUMP resolution, the BLAKE3
+service, witnesses, or commit tracking. It never claims that an arithmetic
+response represents any of those omitted behaviors. The host must validate and
+frame packets, check CRCs, resolve control/memory effects, call BLAKE3, manage
+witnesses/commits, and decompose authorized scalar work into these micro-ops.
+The canonical `asic_core/` full LSC-1 implementation is unchanged.
+
+## Tiny Tapeout pin protocol
+
+`ui_in[7:0]` is RX data and `uo_out[7:0]` is TX data. Bidirectional pins are:
+
+| Pin | Direction | Meaning |
+| --- | --- | --- |
+| `uio[0]` | input | `RX_VALID` |
+| `uio[1]` | output | `RX_READY` |
+| `uio[2]` | output | `TX_VALID` |
+| `uio[3]` | input | `TX_READY` |
+| `uio[4]` | output | `BUSY` |
+| `uio[5]` | output | `FAULT` |
+| `uio[6]` | reserved input | ignored |
+| `uio[7]` | output | one-cycle `DONE_PULSE` |
+
+A byte is accepted only on a rising edge with both VALID and READY high.
+Payload width is determined solely by the accepted opcode; there is no length
+field, delimiter, CRC, or full-packet buffer. The producer must hold RX data
+stable while stalled. TX data remains stable while `TX_VALID && !TX_READY`.
+Exactly one `DONE_PULSE` is emitted when the final response byte is accepted.
+
+`rst_n=0` synchronously cancels partial work, clears outputs/fault, and returns
+to command acceptance. When `ena=0`, all outputs and output-enables are zero,
+no transfer can be accepted, and internal state is frozen. Therefore
+deselect/reselect resumes the same partial operation without duplicating it.
+
+## Physical inclusion rule for MUL
+
+The real 1×1 ttsky26c attempt mapped to 1,616 cells / 17,583.1136 µm² and
+stopped at 128.237% global-placement utilization. Local hierarchy attributes
+1,027 of 1,433 generic cells and 256 of 283 flops to MUL. The smallest
+follow-up is therefore 1×2. MUL remains only if real placement and routing
+succeeds; if it still prevents routing it will be removed, and SET/XOR
+semantics will not be altered to make room.

docs/TAPEOUT.md

@@ -1,11 +1,9 @@
 # Tiny Tapeout target
 
-The target top is `lean_silicon_lsc1` in `asic_core/rtl`, listed by
-`info.yaml`. It has only the standard Tiny Tapeout `ui_in[7:0]`,
-`uo_out[7:0]`, and `uio[7:0]` interface. uio transports byte ready/valid,
-busy/fault, abort, and done as specified in [LSC1_PROTOCOL](LSC1_PROTOCOL.md).
+The ttsky26c integration top is `tt_um_lfglabs_lean_silicon_lsc1` in `src/`.
+It is a thin wrapper around the unchanged `lean_silicon_lsc1` boundary in
+`asic_core/rtl`. See [TINY_TAPEOUT_TTSKY26C](TINY_TAPEOUT_TTSKY26C.md) for the
+complete pin map, workflow, source boundary, and limitations.
 
-Use the official flow only after the v1 packet executor is complete and
-differentially validated. No LSC-1 PPA/tapeout-fit result exists yet. The
-ULX3S is a pin-accurate debug harness; it must not introduce a wide internal
-ASIC bypass.
+No LSC-1 PPA or routed tile-fit result exists yet. The ULX3S remains a separate
+pin-accurate debug harness and is not included in the Tiny Tapeout source list.