[PW_SID:1073337] [01/28] xor: assert that xor_blocks is not call from interrupt context by linux-riscv-bot · Pull Request #1674 · linux-riscv/linux

linux-riscv-bot · 2026-03-27T07:06:47Z

PR for series 1073337 applied to workflow__riscv__fixes

Name: [01/28] xor: assert that xor_blocks is not call from interrupt context
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1073337
Version: 1

Fix various typos in RISC-V architecture code and comments. The following changes are included: - arch/riscv/errata/thead/errata.c: "futher" → "further" - arch/riscv/include/asm/atomic.h: "therefor" → "therefore", "arithmatic" → "arithmetic" - arch/riscv/include/asm/elf.h: "availiable" → "available", "coorespends" → "corresponds" - arch/riscv/include/asm/processor.h: "requries" → "is required" - arch/riscv/include/asm/thread_info.h: "returing" → "returning" - arch/riscv/kernel/acpi.c: "compliancy" → "compliance" - arch/riscv/kernel/ftrace.c: "therefor" → "therefore" - arch/riscv/kernel/head.S: "intruction" → "instruction" - arch/riscv/kernel/mcount-dyn.S: "localtion → "location" - arch/riscv/kernel/module-sections.c: "maxinum" → "maximum" - arch/riscv/kernel/probes/kprobes.c: "reenabled" → "re-enabled" - arch/riscv/kernel/probes/uprobes.c: "probbed" → "probed" - arch/riscv/kernel/soc.c: "extremly" → "extremely" - arch/riscv/kernel/suspend.c: "incosistent" → "inconsistent" - arch/riscv/kvm/tlb.c: "cahce" → "cache" - arch/riscv/kvm/vcpu_pmu.c: "indicies" → "indices" - arch/riscv/lib/csum.c: "implmentations" → "implementations" - arch/riscv/lib/memmove.S: "ammount" → "amount" - arch/riscv/mm/cacheflush.c: "visable" → "visible" - arch/riscv/mm/physaddr.c: "aginst" → "against" Signed-off-by: Sean Chang <seanwascoding@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260212163325.60389-1-seanwascoding@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>

Commit f1a0a37 ("sched/core: Initialize the idle task with preemption disabled") removed a call to preempt_disable(), but not the associated comment. Remove the outdated comment. Fixes: f1a0a37 ("sched/core: Initialize the idle task with preemption disabled") Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-1-8b77aa181530@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>

local_flush_icache_all() only flushes and synchronizes the *instruction* cache, not the data cache. Since RISC-V does have a cbo.flush instruction for data cache flush, clarify the comment to avoid confusion. Fixes: 58661a3 ("riscv: Flush the instruction cache during SMP bringup") Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>

The kaslr_offset() function is a simple accessor that returns kernel_map.virt_offset. This commit change also ensures that kaslr_offset() is consistently available across various kernel configurations without requiring explicit linkage to mm/init.c. Signed-off-by: Austin Kim <austin.kim@lge.com> Link: https://patch.msgid.link/aYwJ76yHaMbbQVJA@adminpc-PowerEdge-R7525 Signed-off-by: Paul Walmsley <pjw@kernel.org>

The following options are required by the kdump crash utility for RISC-V based vmcore file: - kaslr: If the vmcore is generated from a KASLR-enabled Linux kernel, the KASLR offset is required for the crash utility to load the vmcore. Without the proper kaslr option, the crash utility fails to load the vmcore file. - satp: The exact root page table address helps determine the correct base PGD address. With this patch, RISC-V VMCOREINFO ELF notes now include both kaslr and satp information. Signed-off-by: Austin Kim <austin.kim@lge.com> Link: https://patch.msgid.link/aYwKUE3ZzN7/ZY/A@adminpc-PowerEdge-R7525 Signed-off-by: Paul Walmsley <pjw@kernel.org>

Fix several bugs in the RISC-V kgdb implementation: - The element of dbg_reg_def[] that is supposed to pertain to the S1 register embeds instead the struct pt_regs offset of the A1 register. Fix this to use the S1 register offset in struct pt_regs. - The sleeping_thread_to_gdb_regs() function copies the value of the S10 register into the gdb_regs[] array element meant for the S9 register, and copies the value of the S11 register into the array element meant for the S10 register. It also neglects to copy the value of the S11 register. Fix all of these issues. Fixes: fe89bd2 ("riscv: Add KGDB support") Cc: Vincent Chen <vincent.chen@sifive.com> Link: https://patch.msgid.link/fde376f8-bcfd-bfe4-e467-07d8f7608d05@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>

Similarly to commit 8d09e2d ("arm64: patching: avoid early page_to_phys()"), avoid using phys_to_page() for the kernel address case in patch_map(). Since this is called from apply_boot_alternatives() in setup_arch(), and commit 4267739 ("arch, mm: consolidate initialization of SPARSE memory model") has moved sparse_init() to after setup_arch(), phys_to_page() is not available there yet, and it panics on boot with SPARSEMEM on RV32, which does not use SPARSEMEM_VMEMMAP. Reported-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Closes: https://lore.kernel.org/r/20260223144108-dcace0b9-02e8-4b67-a7ce-f263bed36f26@linutronix.de/ Fixes: 4267739 ("arch, mm: consolidate initialization of SPARSE memory model") Suggested-by: Mike Rapoport <rppt@kernel.org> Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Acked-by: Mike Rapoport (Microsoft) <rppt@kernel.org> Tested-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Link: https://patch.msgid.link/20260310-riscv-sparsemem-alternatives-fix-v1-1-659d5dd257e2@iscas.ac.cn [pjw@kernel.org: fix the subject line to align with the patch description] Signed-off-by: Paul Walmsley <pjw@kernel.org>

The BITS variable conveniently allows to simplify the assignment for UTS_MACHINE. Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20260313164012.1153936-2-u.kleine-koenig@baylibre.com Signed-off-by: Paul Walmsley <pjw@kernel.org>

The BIT() macros is used by the validate_v_ptrace() test case, but not defined. Include linux/bits.h to pull in this definition. To ensure that the header in the kernel source is used, add tools/include to the header search path. Fixes: 30eb191 ("selftests: riscv: verify ptrace rejects invalid vector csr inputs") Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-and-tested-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20260309-fix_selftests-v2-1-9d5a553a531e@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>

BIT() is being used in ptrace.h without a definition, resulting in compilation errors in tools/testing/selftests/riscv/cfi/cfitests.c: cfitests.c:101:60: error: implicit declaration of function ‘BIT’ [-Wimplicit-function-declaration] 101 | if ((cfi_reg.cfi_status.cfi_state & CFI_ENABLE_MASK) != CFI_ENABLE_MASK) Include linux/bits.h to resolve this issue. Fixes: 2af7c9c ("riscv/ptrace: expose riscv CFI status and state via ptrace and in core files") Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Link: https://patch.msgid.link/20260309-fix_selftests-v2-3-9d5a553a531e@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>

The cfi selftest was missing a license so add it. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Deepak Gupta <debug@rivosinc.com> Link: https://patch.msgid.link/20260309-fix_selftests-v2-4-9d5a553a531e@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>

Most of the optimized xor_blocks versions require FPU/vector registers, which generally are not supported in interrupt context. Both callers already are in user context, so enforce this at the highest level. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

xor_blocks can't be called from interrupt context, so remove the handling for that. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Commit 2c54b42 ("arm64/xor: use EOR3 instructions when available") changes the definition to __ro_after_init instead of const, but failed to update the external declaration in xor.h. This was not found because xor-neon.c doesn't include <asm/xor.h>, and can't easily do that due to current architecture of the XOR code. Fixes: 2c54b42 ("arm64/xor: use EOR3 instructions when available") Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Since commit c055e3e ("crypto: xor - use ktime for template benchmarking") the benchmarking works just fine even for TT_MODE_INFCPU, so drop the workarounds. Note that for CPUs supporting AVX2, which includes almost everything built in the last 10 years, the AVX2 implementation is forced anyway. CONFIG_X86_32 is always correctly set for UM in arch/x86/um/Kconfig, so don't override it either. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Richard Weinberger <richard@nod.at> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the RAID XOR code to lib/raid/ as it has nothing to do with the crypto API. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Update the to of file comment to be correct and non-redundant, and drop the unused BH_TRACE define. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Originally, the XOR code benchmarked all algorithms at load time, but it has since then been hacked multiple times to allow forcing an algorithm, and then commit 524ccdb ("crypto: xor - defer load time benchmark to a later time") changed the logic to a two-step process or registration and benchmarking, but only when built-in. Rework this, so that the XOR_TRY_TEMPLATES macro magic now always just deals with adding the templates to the list, and benchmarking is always done in a second pass; for modular builds from module_init, and for the built-in case using a separate init call level. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Keep xor.h for the public API, and split the struct xor_block_template definition that is only needed by the xor.ko core and architecture-specific optimizations into a separate xor_impl.h header. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Drop the pretty confusing historic XOR_TRY_TEMPLATES and XOR_SELECT_TEMPLATE, and instead let the architectures provide a arch_xor_init that calls either xor_register to register candidates or xor_force to force a specific implementation. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the generic implementations from asm-generic/xor.h to per-implementaion .c files in lib/raid. This will build them unconditionally even when an architecture forces a specific implementation, but as we'll need at least one generic version for the static_call optimization later on we'll pay that price. Note that this would cause the second xor_block_8regs instance created by arch/arm/lib/xor-neon.c to be generated instead of discarded as dead code, so add a NO_TEMPLATE symbol to disable it for this case. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the optimized XOR code out of line into lib/raid. Note that the giant inline assembly block might be better off as a separate assembly source file now, but I'll leave that to the alpha maintainers. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Magnus Lindholm <linmag7@gmail.com> Tested-by: Magnus Lindholm <linmag7@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the optimized XOR into lib/raid and include it it in the main xor.ko instead of building a separate module for it. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the optimized XOR into lib/raid and include it it in the main xor.ko instead of building a separate module for it. Note that this drops the CONFIG_KERNEL_MODE_NEON dependency, as that is always set for arm64. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. The code should probably be split into separate files for the two implementations, but for now this just does the trivial move. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Move the optimized XOR into lib/raid and include it it in xor.ko instead of unconditionally building it into the main kernel image. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Heiko Carstens <hca@linux.ibm.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2026-03-28T02:50:49Z

Patch 26: "[26/28] xor: pass the entire operation to the low-level ops"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T02:53:19Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 136.18 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:10:21Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1020.72 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:33:18Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1375.36 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:33:45Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.18 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:34:12Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.18 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:34:15Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.77 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:35:42Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 85.18 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:35:43Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:35:45Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
kdoc
Desc: Detects for kdoc errors
Duration: 0.92 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:35:47Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:35:49Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:35:51Z

Patch 27: "[27/28] xor: use static_call for xor_gen"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:38:22Z

Patch 28: "[28/28] xor: add a kunit test case"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 137.22 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T03:57:05Z

Patch 28: "[28/28] xor: add a kunit test case"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1121.31 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:24:03Z

Patch 28: "[28/28] xor: add a kunit test case"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1616.95 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:24:30Z

Patch 28: "[28/28] xor: add a kunit test case"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.20 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:24:59Z

Patch 28: "[28/28] xor: add a kunit test case"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.55 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:25:03Z

Patch 28: "[28/28] xor: add a kunit test case"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.84 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#23: 
new file mode 100644

WARNING: please write a help paragraph that fully describes the config symbol with at least 4 lines
#40: FILE: lib/raid/Kconfig:21:
+config XOR_KUNIT_TEST
+	tristate "KUnit tests for xor_gen" if !KUNIT_ALL_TESTS
+	depends on KUNIT
+	depends on XOR_BLOCKS
+	default KUNIT_ALL_TESTS
+	help
+	  Unit tests for the XOR library functions.
+
+	  This is intended to help people writing architecture-specific
+	  optimized versions.  If unsure, say N.

CHECK: Alignment should match open parenthesis
#111: FILE: lib/raid/xor/tests/xor_kunit.c:34:
+static void xor_ref(void *dest, void **srcs, unsigned int src_cnt,
+		unsigned int bytes)

CHECK: Alignment should match open parenthesis
#197: FILE: lib/raid/xor/tests/xor_kunit.c:120:
+		KUNIT_EXPECT_MEMEQ_MSG(test, test_ref + align,
+				test_dest + align, len,

CHECK: Please use a blank line after function/struct/union/enum declarations
#261: FILE: lib/raid/xor/tests/xor_kunit.c:184:
+};
+kunit_test_suite(xor_test_suite);

total: 0 errors, 2 warnings, 3 checks, 215 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit e78df444b28b ("xor: add a kunit test case") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 2 warnings, 3 checks, 215 lines checked
CHECK: Alignment should match open parenthesis
CHECK: Please use a blank line after function/struct/union/enum declarations
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
WARNING: please write a help paragraph that fully describes the config symbol with at least 4 lines

linux-riscv-bot · 2026-03-28T04:26:28Z

Patch 28: "[28/28] xor: add a kunit test case"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 83.81 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:26:30Z

Patch 28: "[28/28] xor: add a kunit test case"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:26:32Z

Patch 28: "[28/28] xor: add a kunit test case"
kdoc
Desc: Detects for kdoc errors
Duration: 0.91 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:26:34Z

Patch 28: "[28/28] xor: add a kunit test case"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:26:35Z

Patch 28: "[28/28] xor: add a kunit test case"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2026-03-28T04:26:37Z

Patch 28: "[28/28] xor: add a kunit test case"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.30 seconds
Result: PASS

Sean Chang and others added 30 commits February 18, 2026 20:49

Adding CI files

c315cbf

arm/xor: remove in_interrupt() handling

435f786

xor_blocks can't be called from interrupt context, so remove the handling for that. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

xor: move to lib/raid/

216a771

Move the RAID XOR code to lib/raid/ as it has nothing to do with the crypto API. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

xor: small cleanups

e0326d2

Update the to of file comment to be correct and non-redundant, and drop the unused BH_TRACE define. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

arm: move the XOR code to lib/raid/

ec9a3c0

Move the optimized XOR into lib/raid and include it it in the main xor.ko instead of building a separate module for it. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

loongarch: move the XOR code to lib/raid/

1faa0d5

Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

powerpc: move the XOR code to lib/raid/

5b4e21f

Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

riscv: move the XOR code to lib/raid/

881a633

Move the optimized XOR into lib/raid and include it it in xor.ko instead of always building it into the main kernel image. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot force-pushed the workflow__riscv__fixes branch 3 times, most recently from b8c30cd to 2830afe Compare April 4, 2026 01:26

linux-riscv-bot closed this Apr 4, 2026

linux-riscv-bot deleted the pw1073337 branch April 4, 2026 01:26

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