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5d9d634
riscv: fix various typos in comments and code
Feb 19, 2026
37a14b6
riscv: smp: Remove outdated comment about disabling preemption
dramforever Feb 19, 2026
4dd1663
riscv: smp: Clarify comment "cache" -> "instruction cache"
dramforever Feb 19, 2026
37f1490
riscv: move kaslr_offset() to page.h as a static inline function
Feb 19, 2026
097da80
riscv: export kaslr offset and satp in VMCOREINFO ELF notes
Feb 19, 2026
1121200
riscv: kgdb: fix several debug register assignment bugs
Feb 19, 2026
3a87650
riscv: patch: Avoid early phys_to_page()
dramforever Mar 10, 2026
1351ac7
riscv: Simplify assignment for UTS_MACHINE
ukleinek Mar 13, 2026
e93c297
selftests: riscv: Add definition of BIT() macro
thecharlesjenkins Mar 10, 2026
b1b59c4
riscv: ptrace: Fix BIT() compilation issues
thecharlesjenkins Mar 10, 2026
5ccc568
selftests: riscv: Add license to cfi selftest
thecharlesjenkins Mar 10, 2026
c315cbf
Adding CI files
Mar 21, 2026
4dcc558
xor: assert that xor_blocks is not call from interrupt context
Mar 27, 2026
435f786
arm/xor: remove in_interrupt() handling
Mar 27, 2026
647c815
arm64/xor: fix conflicting attributes for xor_block_template
Mar 27, 2026
38e9af6
um/xor: cleanup xor.h
Mar 27, 2026
216a771
xor: move to lib/raid/
Mar 27, 2026
e0326d2
xor: small cleanups
Mar 27, 2026
f25e9b0
xor: cleanup registration and probing
Mar 27, 2026
3a25281
xor: split xor.h
Mar 27, 2026
2a095a8
xor: remove macro abuse for XOR implementation registrations
Mar 27, 2026
77c1f0f
xor: move generic implementations out of asm-generic/xor.h
Mar 27, 2026
26da3d9
alpha: move the XOR code to lib/raid/
Mar 27, 2026
ec9a3c0
arm: move the XOR code to lib/raid/
Mar 27, 2026
9386ad3
arm64: move the XOR code to lib/raid/
Mar 27, 2026
1faa0d5
loongarch: move the XOR code to lib/raid/
Mar 27, 2026
5b4e21f
powerpc: move the XOR code to lib/raid/
Mar 27, 2026
881a633
riscv: move the XOR code to lib/raid/
Mar 27, 2026
23894f1
sparc: move the XOR code to lib/raid/
Mar 27, 2026
edae1aa
s390: move the XOR code to lib/raid/
Mar 27, 2026
978434e
x86: move the XOR code to lib/raid/
Mar 27, 2026
f2f1b6b
xor: avoid indirect calls for arm64-optimized ops
Mar 27, 2026
9f483e3
xor: make xor.ko self-contained in lib/raid/
Mar 27, 2026
ec8ac90
xor: add a better public API
Mar 27, 2026
3879959
xor: add a better public API
Mar 27, 2026
e531192
async_xor: use xor_gen
Mar 27, 2026
6dc739d
btrfs: use xor_gen
Mar 27, 2026
79e301b
xor: pass the entire operation to the low-level ops
Mar 27, 2026
edaeea9
xor: use static_call for xor_gen
Mar 27, 2026
e78df44
xor: add a kunit test case
Mar 27, 2026
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29 changes: 29 additions & 0 deletions .github/scripts/build_ubuntu_defconfig.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
#!/bin/bash
# SPDX-FileCopyrightText: 2024 Rivos Inc.
#
# SPDX-License-Identifier: Apache-2.0

set -euox pipefail
d=$(dirname "${BASH_SOURCE[0]}")
. $d/series/utils.sh

logs=$(get_logs_dir)
f=${logs}/build_ubuntu_defconfig.log

date -Iseconds | tee -a ${f}
echo "Build an ubuntu kernel" | tee -a ${f}
echo "Top 16 commits" | tee -a ${f}
git log -16 --abbrev=12 --pretty="commit %h (\"%s\")" | tee -a ${f}

kernel_base_sha=$(git log -1 --pretty=%H $(git log -1 --reverse --pretty=%H .github)^)
echo "build_name $(git describe --tags ${kernel_base_sha})" | tee -a ${f}
build_name=$(git describe --tags ${kernel_base_sha})

# Build the kernel that will run LTP
export CI_TRIPLE="riscv64-linux-gnu"
cp $d/series/kconfigs/ubuntu_defconfig arch/riscv/configs/
$d/series/kernel_builder.sh rv64 testsuites plain gcc | tee -a ${f}

kernel_dir="/build/$(gen_kernel_name rv64 testsuites plain gcc)"
echo $build_name > $kernel_dir/kernel_version
#tar cJvf --exclude $(basename $kernel_path) modules.tar.xz /build/$(gen_kernel_name rv64 testsuites plain gcc)/
2 changes: 2 additions & 0 deletions .github/scripts/ci/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from .base import Base, EndTest, Verdict, submit_pw_check
from .shelltest import ShellTest
120 changes: 120 additions & 0 deletions .github/scripts/ci/base.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,120 @@
from abc import ABC, abstractmethod
from enum import Enum
import time
import sys

from libs import utils

sys.path.insert(0, '../libs')
from libs import log_debug

class Verdict(Enum):
PENDING = 0
PASS = 1
FAIL = 2
ERROR = 3
SKIP = 4
WARNING = 5


class EndTest(Exception):
"""
End of Test
"""

class Base(ABC):
"""
Base class for CI Tests.
"""
def __init__(self):
self.start_time = 0
self.end_time = 0
self.verdict = Verdict.PENDING
self.output = ""

def success(self):
self.end_timer()
self.verdict = Verdict.PASS

def error(self, msg):
self.verdict = Verdict.ERROR
self.output = msg
self.end_timer()
raise EndTest

def warning(self, msg):
self.verdict = Verdict.WARNING
self.output = msg
self.end_timer()

def skip(self, msg):
self.verdict = Verdict.SKIP
self.output = msg
self.end_timer()
raise EndTest

def add_failure(self, msg):
self.verdict = Verdict.FAIL
if not self.output:
self.output = msg
else:
self.output += "\n" + msg

def add_failure_end_test(self, msg):
self.add_failure(msg)
self.end_timer()
raise EndTest

def start_timer(self):
self.start_time = time.time()

def end_timer(self):
self.end_time = time.time()

def elapsed(self):
if self.start_time == 0:
return 0
if self.end_time == 0:
self.end_timer()
return self.end_time - self.start_time

def log_err(self, msg):
utils.log_error(f"CI: {self.name}: {msg}")

def log_info(self, msg):
utils.log_info(f"CI: {self.name}: {msg}")

def log_dbg(self, msg):
utils.log_debug(f"CI: {self.name}: {msg}")

@abstractmethod
def run(self, worktree=None):
"""
The child class should implement run() method
If the test fail, it should raise the EndTest exception
"""
pass

@abstractmethod
def post_run(self):
"""
The child class should implement post_run() method
"""
pass


def submit_pw_check(pw, patch, name, verdict, desc, url=None, dry_run=False):

utils.log_debug(f"Submitting the result to PW: dry_run={dry_run}")

if not dry_run:
state = 0

if verdict == Verdict.PASS:
state = 1
if verdict == Verdict.WARNING:
state = 2
if verdict == Verdict.FAIL:
state = 3

pw.post_check(patch, name, state, desc, url)
67 changes: 67 additions & 0 deletions .github/scripts/ci/shelltest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
from gettext import install
import os
import sys

sys.path.insert(0, '../libs')
from libs import RepoTool, cmd_run

from ci import Base, Verdict, EndTest, submit_pw_check

class ShellTest(Base):
"""Run shell test class
This class runs a shell based test
"""

def __init__(self, ci_data, patch, name, desc, sh):

# Common
self.name = name
self.desc = desc
self.ci_data = ci_data

self.sh = sh
self.patch = patch

super().__init__()

self.log_dbg("Initialization completed")

def run(self, worktree=None):

self.log_dbg("Run")
self.start_timer()

current_script_path = os.path.dirname(os.path.abspath(__file__))

cwd = worktree if worktree else self.ci_data.src_dir
cmd = ["bash", f"{current_script_path}/../pw_tests/{self.sh}"]
(ret, stdout, stderr) = cmd_run(cmd, cwd=cwd)

if ret == 0:
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.PASS,
self.name,
None, self.ci_data.config['dry_run'])
self.success()
elif ret == 250:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-WARNING",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.WARNING,
self.name,
url, self.ci_data.config['dry_run'])
self.warning(stdout + '\n' + stderr)
else:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-FAIL",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.FAIL,
self.name,
url, self.ci_data.config['dry_run'])
self.error(stdout + '\n' + stderr)

def post_run(self):

self.log_dbg("Post Run...")
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