[PW_SID:1078268] riscv: dts: sophgo: reduce SG2042 MSI count to 16#1738
[PW_SID:1078268] riscv: dts: sophgo: reduce SG2042 MSI count to 16#1738linux-riscv-bot wants to merge 1 commit into
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The SG2042 MSI controller has one 32-bit doorbell register, and each bit corresponds to an interrupt. At a glance, it seems that the MSI controller can support 32 interrupts; however the PCI MSI capability only supports 16-bit messages, which makes the high 16 interrupts unusable in such way. Reduce the MSI count to 16 to prevent producing MSI message values that cannot fit 16-bit integers. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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Patch 1: "riscv: dts: sophgo: reduce SG2042 MSI count to 16" |
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PR for series 1078268 applied to workflow__riscv__fixes
Name: riscv: dts: sophgo: reduce SG2042 MSI count to 16
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1078268
Version: 1