[PW_SID:1078443] riscv: Generate riscv instruction functions by linux-riscv-bot · Pull Request #1747 · linux-riscv/linux

linux-riscv-bot · 2026-04-10T01:36:03Z

PR for series 1078443 applied to workflow__riscv__fixes

Name: riscv: Generate riscv instruction functions
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1078443
Version: 1

Eliminate the need to hand-write riscv instructions by using a shell script to autogenerate a header from an instruction table. This is modeled after the syscall table infrastructure. The table is generated externally by riscv-unified-db [1], but is in a simple format to make it possible to use other tools or modify manually. [1] https://github.com/riscv-software-src/riscv-unified-db Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the alternatives patching code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the code that is decoding instructions for the use of kgdb single stepping to use the generated instruction headers instead of the hand-written instruction functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the code that is decoding instruction for the use of kprobes to use the generated instruction headers instead of the hand-written instruction functions. With the more granular instruction support, split the decoding of branches into their own functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the code that is decoding cfi instructions to use the generated instruction headers. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the misaligned loads/store code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the csr parsing code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

KVM MMIO emulation failed to sign extend any signed reads and at the same time also unsuccessfully attempted to sign extend reads using lbu. Remove the shifting for lbu to avoid sign extension for that instruction and cast the data to a signed long instead of an unsigned long to allow for sign extension. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Create a KVM test device to help verify mmio reads and write emulation. This is a simple device that will store the data in a buffer on writes and echo back that stored data on a read. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Use the test KVM device to validate that reads and writes to a device are properly emulated by KVM. This test checks all load and store instructions that are emulated by KVM. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the mmio emulation code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

To test the riscv kvm implementation of emulated CSRs, add support to emulate the vsscratch csr when CONFIG_RISCV_KVM_TEST_CSR is set. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Introduce a kvm test that uses the emulated test csr to validate that all emulated reads/writes to csrs function as expected. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the csr emulation code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Migrate the kexec relocation code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

All usages of hard-coded riscv instruction have been migrated over to the generated instruction headers so the old macros can be deleted. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2026-04-10T01:42:29Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 138.45 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:01:28Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1137.24 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:29:23Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1673.48 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:29:51Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.83 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:30:19Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 26.87 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:30:24Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 3.37 seconds
Result: WARNING
Output:

WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#154: 
new file mode 100644

WARNING: line length of 127 exceeds 100 columns
#1602: FILE: arch/riscv/tools/insn_tbl.sh:19:
+#                             all instruction variables in the form of <var>[-<sign_extend>-][<<left_shift><][!<constraint>...]

WARNING: line length of 114 exceeds 100 columns
#1603: FILE: arch/riscv/tools/insn_tbl.sh:20:
+#                             if the variable requires sign extension, surround the index to sign extend at in '-'

WARNING: line length of 107 exceeds 100 columns
#1604: FILE: arch/riscv/tools/insn_tbl.sh:21:
+#                             if the variable requires left shifting, surround the left shift amount in '<'

WARNING: line length of 107 exceeds 100 columns
#1611: FILE: arch/riscv/tools/insn_tbl.sh:28:
+#                                 ! mark 'num' as an invalid input for this variable, any number may appear

WARNING: line length of 138 exceeds 100 columns
#1743: FILE: arch/riscv/tools/insn_tbl.sh:160:
+                    constraints="${constraints}(riscv_insn_${formatted_inst_name}_extract_${variable_name}(${insn}) != ${constraint}) && "

WARNING: line length of 147 exceeds 100 columns
#1773: FILE: arch/riscv/tools/insn_tbl.sh:190:
+                extract="${extract} | ((${insn}${first_shift:+ >> }${first_shift} & GENMASK($((len - 1)), 0))${second_shift:+ << }${second_shift})"

WARNING: line length of 146 exceeds 100 columns
#1775: FILE: arch/riscv/tools/insn_tbl.sh:192:
+                insert="${insert} | (((${var}${second_shift:+ >> }${second_shift}) & GENMASK($((len - 1)), 0))${first_shift:+ << }${first_shift})"

WARNING: line length of 133 exceeds 100 columns
#1795: FILE: arch/riscv/tools/insn_tbl.sh:212:
+            echo "static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn})"

WARNING: line length of 141 exceeds 100 columns
#1799: FILE: arch/riscv/tools/insn_tbl.sh:216:
+            echo "static __always_inline void riscv_insn_${formatted_inst_name}_insert_${variable_name}(u${size} *${insn}, ${type}32 ${var})"

WARNING: line length of 260 exceeds 100 columns
#1806: FILE: arch/riscv/tools/insn_tbl.sh:223:
+                invalid_inst_functions="${invalid_inst_functions}static __always_inline ${type}${size} riscv_insn_${formatted_inst_name}_extract_${variable_name}(u${size} ${insn}) {\n\tpanic(\"${name} is not supported on non ${only_base}-bit systems.\");\n}\n"

WARNING: line length of 111 exceeds 100 columns
#1809: FILE: arch/riscv/tools/insn_tbl.sh:226:
+            make="${make}	riscv_insn_${formatted_inst_name}_insert_${variable_name}(&${insn}, ${var});\n"

total: 0 errors, 12 warnings, 0 checks, 1782 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 827967194aa0 ("riscv: Introduce instruction table generation") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 12 warnings, 0 checks, 1782 lines checked
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
WARNING: line length of 107 exceeds 100 columns
WARNING: line length of 111 exceeds 100 columns
WARNING: line length of 114 exceeds 100 columns
WARNING: line length of 127 exceeds 100 columns
WARNING: line length of 133 exceeds 100 columns
WARNING: line length of 138 exceeds 100 columns
WARNING: line length of 141 exceeds 100 columns
WARNING: line length of 146 exceeds 100 columns
WARNING: line length of 147 exceeds 100 columns
WARNING: line length of 260 exceeds 100 columns

linux-riscv-bot · 2026-04-10T02:31:49Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 83.31 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:31:50Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:31:53Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
kdoc
Desc: Detects for kdoc errors
Duration: 0.86 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:31:54Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:31:56Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:31:58Z

Patch 1: "[02/16] riscv: alternatives: Use generated instruction headers for patching code"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.32 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:34:29Z

Patch 2: "[03/16] riscv: kgdb: Use generated instruction headers"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 136.14 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T02:53:19Z

Patch 2: "[03/16] riscv: kgdb: Use generated instruction headers"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1128.72 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T12:53:05Z

Patch 14: "[15/16] riscv: kexec: Use generated instruction headers for kexec relocations"
kdoc
Desc: Detects for kdoc errors
Duration: 0.91 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T12:53:07Z

Patch 14: "[15/16] riscv: kexec: Use generated instruction headers for kexec relocations"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T12:53:09Z

Patch 14: "[15/16] riscv: kexec: Use generated instruction headers for kexec relocations"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T12:53:11Z

Patch 14: "[15/16] riscv: kexec: Use generated instruction headers for kexec relocations"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.31 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T12:55:44Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 138.41 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:14:32Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1126.95 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:41:58Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1643.96 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:42:26Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.91 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:42:54Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 27.11 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:42:57Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.77 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:44:22Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 83.94 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:44:24Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:44:27Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
kdoc
Desc: Detects for kdoc errors
Duration: 0.83 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:44:29Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
module-param
Desc: Detect module_param changes
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:44:31Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:44:32Z

Patch 15: "[16/16] riscv: Remove unused instruction headers"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.32 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T13:47:06Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 139.50 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:06:04Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1136.17 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:33:50Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1663.75 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:34:17Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 25.90 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:34:46Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 27.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:34:48Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.78 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:36:15Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 84.58 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:36:16Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:36:19Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
kdoc
Desc: Detects for kdoc errors
Duration: 0.90 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:36:21Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:36:23Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-04-10T14:36:25Z

Patch 16: "[1/16] riscv: Introduce instruction table generation"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.32 seconds
Result: PASS

thecharlesjenkins added 16 commits April 10, 2026 01:36

riscv: cfi: Use generated instruction headers

50155a2

Migrate the code that is decoding cfi instructions to use the generated instruction headers. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot closed this Apr 16, 2026

linux-riscv-bot deleted the pw1078443 branch April 16, 2026 01:56

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