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[PW_SID:1080868] bpf, arm64/riscv: Remove redundant icache flush after pack allocator finalize #1763

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[PW_SID:1080868] bpf, arm64/riscv: Remove redundant icache flush after pack allocator finalize #1763

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7b56b51
bpf, arm64: Remove redundant bpf_flush_icache() after pack allocator …
puranjaymohan Apr 13, 2026
e2a9a8e
bpf, riscv: Remove redundant bpf_flush_icache() after pack allocator …
puranjaymohan Apr 13, 2026
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12 changes: 0 additions & 12 deletions arch/arm64/net/bpf_jit_comp.c
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,6 @@

#include <asm/asm-extable.h>
#include <asm/byteorder.h>
#include <asm/cacheflush.h>
#include <asm/cpufeature.h>
#include <asm/debug-monitors.h>
#include <asm/insn.h>
Expand Down Expand Up @@ -1961,11 +1960,6 @@ static int validate_ctx(struct jit_ctx *ctx)
return 0;
}

static inline void bpf_flush_icache(void *start, void *end)
{
flush_icache_range((unsigned long)start, (unsigned long)end);
}

static void priv_stack_init_guard(void __percpu *priv_stack_ptr, int alloc_size)
{
int cpu, underflow_idx = (alloc_size - PRIV_STACK_GUARD_SZ) >> 3;
Expand Down Expand Up @@ -2204,12 +2198,6 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
prog = orig_prog;
goto out_off;
}
/*
* The instructions have now been copied to the ROX region from
* where they will execute. Now the data cache has to be cleaned to
* the PoU and the I-cache has to be invalidated for the VAs.
*/
bpf_flush_icache(ro_header, ctx.ro_image + ctx.idx);
} else {
jit_data->ctx = ctx;
jit_data->ro_image = ro_image_ptr;
Expand Down
6 changes: 0 additions & 6 deletions arch/riscv/net/bpf_jit.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@

#include <linux/bpf.h>
#include <linux/filter.h>
#include <asm/cacheflush.h>

/* verify runtime detection extension status */
#define rv_ext_enabled(ext) \
Expand Down Expand Up @@ -105,11 +104,6 @@ static inline void bpf_fill_ill_insns(void *area, unsigned int size)
memset(area, 0, size);
}

static inline void bpf_flush_icache(void *start, void *end)
{
flush_icache_range((unsigned long)start, (unsigned long)end);
}

/* Emit a 4-byte riscv instruction. */
static inline void emit(const u32 insn, struct rv_jit_context *ctx)
{
Expand Down
7 changes: 0 additions & 7 deletions arch/riscv/net/bpf_jit_core.c
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Expand Up @@ -183,13 +183,6 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
prog = orig_prog;
goto out_offset;
}
/*
* The instructions have now been copied to the ROX region from
* where they will execute.
* Write any modified data cache blocks out to memory and
* invalidate the corresponding blocks in the instruction cache.
*/
bpf_flush_icache(jit_data->ro_header, ctx->ro_insns + ctx->ninsns);
for (i = 0; i < prog->len; i++)
ctx->offset[i] = ninsns_rvoff(ctx->offset[i]);
bpf_prog_fill_jited_linfo(prog, ctx->offset);
Expand Down