Welcome to my personal collection of mini FPGA-based projects! This repository contains a growing set of simple yet functional digital design modules built with Verilog/SystemVerilog. Each project includes synthesisable design files and corresponding testbenches to verify functionality.
-
ALU
A basic Arithmetic and Logic Unit supporting essential operations. -
Barrel Shifter
Implements logical and rotational shift operations for variable distances. -
LED Blink
Simple LED blinker using counters and clock division. -
Integrated Up-Down Counter
A binary counter module with control for both up and down counting.
📹 Each project is verified in simulation and also tested on hardware. Relevant videos and photos demonstrating working conditions are included.
Each project folder typically contains:
design.v– Synthesisable Verilog/SystemVerilog sourcetb.v– Testbench for simulationdocs/– (Optional) Images or video links showing the working hardware
This repo is a work in progress. I will continue adding more mini projects over time. Stay tuned !
These projects are part of my learning and exploration with FPGA design, targeted mainly at development boards like [Nexys Artix-7 100T FPGA board] Feel free to explore, suggest improvements, or fork for your own use!
For suggestions, collaborations or questions:
- GitHub Issues or Discussions tab
- [naveenau2023@gmail.com]
MIT – Feel free to use and modify with attribution.