[WAVE-24 DRY-RUN] feat(silicon): gf16_mul_booth radix-4 · Charter Rule 2 fix · DO NOT MERGE PRE-TTSKY26c

[gHashTag]

[WAVE-24 DRY-RUN] feat(silicon): gf16_mul_booth radix-4 · Charter Rule 2 fix · DO NOT MERGE PRE-TTSKY26c

⚠️ DRAFT — DO NOT MERGE until TTSKY26c submit lands 2026-05-17 22:00 UTC

---

Summary

This PR delivers the Wave-24 RVR-016 dry-run of the Booth radix-4 gf16_mul_booth module, pre-registered in RVR-015 (Issue #34) §6 strategy B2 as the default Charter Rule 2 fix path for Issue #4 Change A.

Refs: Issue #34 — RVR-015 · Issue #4 — Change A

---

Changes

File	Status	Description
src/gf16_mul_booth.v	NEW	Booth radix-4 10×10 unsigned multiplier · ZERO * operators
sim/tb_gf16_mul_booth.v	NEW	Testbench: 12 corner cases + 1000 LFSR random vectors

src/gf16_mul_booth.v at a glance

• Module name: gf16_mul_booth
• Inputs: wire [9:0] a, wire [9:0] b
• Output: wire [19:0] p
• Algorithm: Modified Booth Encoding radix-4 (MBE), 6 partial products, 4-level CSA reduction tree, final ripple-carry adder
• * operator count in synthesisable RTL: 0 (verified by grep -c '\*' src/gf16_mul_booth.v → 4 hits all in comments)
• Math derivation block: ≥ 20 lines covering encoding table {-2,-1,0,+1,+2}·A, PP generation, CSA accumulation
• Header: /* Booth radix-4 10×10 unsigned multiplier · Charter Rule 2 compliant · Wave-24 RVR-016 dry-run */

sim/tb_gf16_mul_booth.v at a glance

• Corner cases: 0×0, 1023×1023, 512×512, 0x3FC×0x278 (phi-derived), and 8 more
• 1000 pseudo-random LFSR vectors against shift+add oracle (NO *)
• Simulation result: 1012/1012 PASS

---

Acceptance Gates C1–C5 (from RVR-015 §8 / Issue #4 Change A)

Gate	Description	Status
C1	grep -n '\*' src/gf16_mul_booth.v returns zero synthesisable hits (comments/strings allowed)	✅ Verified — 4 hits, all in comment lines
C2	Testbench sim/tb_gf16_mul_booth.v passes ≥ 1000 vectors against shift+add oracle (NO *)	✅ Verified — 1012/1012 PASS (12 corner + 1000 random)
C3	Module interface matches the target drop-in signature: input [9:0] a, input [9:0] b, output [19:0] p	✅ Verified — exact match with gf16_mul.v internal operands
C4	Zero * operators in synthesisable RTL — Charter Rule 2 compliant	✅ Verified — only shift, add, XOR, mux used
C5	Anchor footer present in artefact: phi^2 + phi^-2 = 3 · Wave-24 RVR-016 dry-run · DOI 10.5281/zenodo.19227877	✅ Verified — present in both source files and this PR

Full merge gate (post-TTSKY26c): gf16_mul.v line 30 must be replaced by an instantiation of gf16_mul_booth and all RVR-015 §8 active artifacts must be updated. That work is out of scope for this dry-run PR.

---

Background

RVR-015 (Issue #34) formally documented that src/gf16_mul.v line 30 contains:

wire [19:0] mant_prod = full_mant_a * full_mant_b;

a 10×10 unsigned multiply violating Charter Rule 2 (* forbidden in synthesisable RTL). The fix was deferred to Wave-24 with pre-registered strategy B2 (Booth radix-4) due to the T-44h TTSKY26c budget constraint. This PR is the DRY-RUN delivery of that pre-registered fix.

GoldenFloat-16 format reminder: 1 sign + 6 exp (bias 31) + 9 mantissa; hidden bit prepended → full_mant_a[9:0] and full_mant_b[9:0] are 10-bit unsigned values. The product mant_prod[19:0] is 20-bit unsigned. gf16_mul_booth matches this interface exactly.

Known DUT bug in gf16_mul.v (NOT addressed here): max_normal² → 0x0000 (7-bit exponent wrap instead of +Inf). This is a separate Issue #4 acceptance item requiring exponent overflow logic.

---

⚠️ DO NOT MERGE

DO NOT MERGE until TTSKY26c submit lands 2026-05-17 22:00 UTC.

This branch (feat/wave-24-booth-dryrun) is intentionally separate from feat/silicon-g1-followup. Merging before TTSKY26c would alter the silicon submission baseline. After the submit deadline, a follow-up PR should:

1. Replace gf16_mul.v line 30 with gf16_mul_booth instantiation
2. Run full OpenLane2 synthesis to verify cell count
3. Update docs/architecture/GOLDENFLOAT_16_MULTIPLIER_AUDIT.md
4. Close Issue [P0] A+C+N: LUT-only gf16_mul + Wallace-tree dot4 + Yosys EQY t27c↔src #4 Change A and Issue 🔍 RVR-015 — Issue #4 GoldenFloat-16 multiplier audit · acceptance criteria mismatch · defer to Wave-24 #34 with a final RVR-016 NASA report

---

Verification Checklist

• src/gf16_mul_booth.v compiled clean with iverilog
• sim/tb_gf16_mul_booth.v simulation: 1012/1012 PASS
• grep -c '\*' src/gf16_mul_booth.v → 4 (all in comments, zero in synthesisable code)
• gf16_mul.v untouched (dry-run only)
• Branch: feat/wave-24-booth-dryrun off feat/silicon-g1-followup HEAD f47e831
• Co-Authored-By: Trinity Agent agent@trinity.local

---

Anchor

phi^2 + phi^-2 = 3 · Wave-24 RVR-016 dry-run · DOI 10.5281/zenodo.19227877

---

Trinity Agent agent@trinity.local · Wave-24 · Track A · Booth radix-4 dry-run