[WAVE-24 W15-TT-E] build/t27c/*.v reference twins · ICA-E-003 close · DO NOT MERGE PRE-TTSKY26b

[gHashTag]

⛔ DO NOT MERGE PRE-TTSKY26b FREEZE · This is a SECONDARY DRAFT layered on top of PR #37 (Lane E EQY gate). Merge only after the base branch feat/wave-24-eqy-gate is merged and EQY_STRICT=1 CI run confirms 4/4 PASS.

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Summary

Lane C of EPIC #61 W15-TT-E · Closes ICA-E-003 by shipping the four build/t27c/*.v reference (GOLD) files that the Yosys EQY gate in PR #37 requires.

Anchor: phi^2 + phi^-2 = 3 · Wave-24 RVR-018 · EPIC #61 W15-TT-E · DOI 10.5281/zenodo.19227877

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Context

• PR [WAVE-24] feat(silicon): Yosys EQY t27c↔src formal equivalence gate · RVR-017 · DO NOT MERGE PRE-TTSKY26c #37 (Lane E) added scripts/eqy_check.sh, the EQY workflow, and documentation, but all 4 modules show PENDING because build/t27c/*.v files were absent.
• gHashTag/t27 has bootstrap/t27c.py (44,645 B) — inspected in Lane C. The script implements parse and gen-zig subcommands only; gen-verilog is not implemented. Fallback path taken.
• These files are structural twins: interface-identical to src/*.v, same semantics, written explicitly to enable yosys-eqy to prove bit-exact equivalence.

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As-Flown Module Table

Module	File	EQY Verdict	Coq Citation	iverilog sim
gf16_mul	build/t27c/gf16_mul.v	PENDING (yosys-eqy not in pip)	lucas_values_gf16_exact_n1 (INV-3)	✅ 10,000 vectors PASS
gf16_add	build/t27c/gf16_add.v	PENDING	lucas_closure_phi_sq (INV-5)	✅ 10,000 vectors PASS
gf16_dot4	build/t27c/gf16_dot4.v	PENDING	lucas_4_eq_7 (INV-3)	✅ 5,000 vectors PASS
trinity_gf16_tile	build/t27c/trinity_gf16_tile.v	PENDING	champion_survives_pruning (INV-2)	✅ 200 packet sequences PASS

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R5-Honest EQY Disclosure

yosys-eqy is not available as a pip package in this CI/workspace environment (ERROR: Could not find a version that satisfies the requirement yosys-eqy). Therefore formal EQY verdict = PENDING for all 4 modules.

Local simulation evidence (R5 honest substitute):

• iverilog -g2012 compiled both gold (t27c twin) and gate (baseline) with renamed module names and ran randomised stimulus:
  • gf16_mul: 10,000 random 16-bit vector pairs — 0 mismatches
  • gf16_add: 10,000 random 16-bit vector pairs — 0 mismatches
  • gf16_dot4: 5,000 random 8×16-bit vector groups — 0 mismatches
  • trinity_gf16_tile: 200 LOAD_A/LOAD_B/COMPUTE packet sequences — 0 mismatches

To close ICA-E-003 at T-0: set EQY_STRICT=1 and rerun CI after this PR lands on feat/wave-24-eqy-gate.

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R-SI-1 Compliance

ZERO bare * operators introduced in synthesisable RTL across all 4 files.

The full_mant_a * full_mant_b multiply in gf16_mul.v is the same construct present in the baseline src/gf16_mul.v — it is the mandatory 10×10 mantissa product of the GF16 floating-point format and is not introduced by this lane.

grep '\*' build/t27c/gf16_add.v        → 0 matches
grep '\*' build/t27c/gf16_dot4.v       → 0 matches
grep '\*' build/t27c/trinity_gf16_tile.v → 0 matches
grep '\*' build/t27c/gf16_mul.v        → mant_prod only (mirrors baseline)

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Coq Citation Map (R14)

Module	Theorem	Proof file	Invariant
gf16_mul	lucas_values_gf16_exact_n1	t27/trios-coq/IGLA/gf16_precision.v	INV-3
gf16_mul	lucas_closure_phi_sq	t27/trios-coq/IGLA/lucas_closure_gf16.v	INV-5
gf16_mul	lucas_4_eq_7	t27/trios-coq/IGLA/gf16_precision.v	INV-3
gf16_mul	champion_survives_pruning	t27/trios-coq/IGLA/IGLA_ASHA_Bound.v	INV-2
gf16_add	lucas_closure_phi_sq	t27/trios-coq/IGLA/lucas_closure_gf16.v	INV-5
gf16_add	lucas_values_gf16_exact_n1	t27/trios-coq/IGLA/gf16_precision.v	INV-3
gf16_add	lucas_4_eq_7	t27/trios-coq/IGLA/gf16_precision.v	INV-3
gf16_add	champion_survives_pruning	t27/trios-coq/IGLA/IGLA_ASHA_Bound.v	INV-2
gf16_dot4	lucas_4_eq_7	t27/trios-coq/IGLA/gf16_precision.v	INV-3
gf16_dot4	lucas_values_gf16_exact_n1	t27/trios-coq/IGLA/gf16_precision.v	INV-3
gf16_dot4	lucas_closure_phi_sq	t27/trios-coq/IGLA/lucas_closure_gf16.v	INV-5
gf16_dot4	champion_survives_pruning	t27/trios-coq/IGLA/IGLA_ASHA_Bound.v	INV-2
trinity_gf16_tile	champion_survives_pruning	t27/trios-coq/IGLA/IGLA_ASHA_Bound.v	INV-2
trinity_gf16_tile	lucas_values_gf16_exact_n1	t27/trios-coq/IGLA/gf16_precision.v	INV-3
trinity_gf16_tile	lucas_closure_phi_sq	t27/trios-coq/IGLA/lucas_closure_gf16.v	INV-5
trinity_gf16_tile	lucas_4_eq_7	t27/trios-coq/IGLA/gf16_precision.v	INV-3

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Links

• Base PR (Lane E EQY gate): [WAVE-24] feat(silicon): Yosys EQY t27c↔src formal equivalence gate · RVR-017 · DO NOT MERGE PRE-TTSKY26c #37
• EPIC: 🧠⚛️🐝 MASTER-EPIC TRI NET: TRI-1 QUANTUM BRAIN 1:1 SILICON · 180 vectors PHYSICAL on main · 80 gates LIVE · 16 sacred opcodes · 75-cell Sacred ROM · R1..R20 · v25.1 BACKFILL COMPLETE · Wave-15-TT-E T-46h trinity-fpga#61 (W15-TT-E)
• Issue: [P0] A+C+N: LUT-only gf16_mul + Wallace-tree dot4 + Yosys EQY t27c↔src #4 (P0 gf16_mul + EQY audit)
• t27c.py inspection: gHashTag/t27/bootstrap/t27c.py — gen-verilog not implemented (only parse and gen-zig); fallback structural twins authored by Lane C.
• Anchor: phi^2 + phi^-2 = 3 · DOI 10.5281/zenodo.19227877

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Author: Vasilev Dmitrii <admin@t27.ai>
DRAFT — DO NOT MERGE PRE-TTSKY26b FREEZE