[WAVE-24 W15-TT-E] feat(silicon): TRI-1 Nano 1x1 single-tile top · EPIC #61 · DO NOT MERGE PRE-TTSKY26b

[gHashTag]

⚠️ DO NOT MERGE PRE-TTSKY26b FREEZE 2026-05-17 22:00 UTC

---

TRI-1 Nano 1×1 — Single-Tile TinyTapeout Top

Lane: NANO-RTL · EPIC: #61 W15-TT-E · Wave: Wave-24 RVR-018
Branch: feat/nano-rtl-w15e → main
Author: Vasilev Dmitrii <admin@t27.ai>
Submitted: 2026-05-15 15:36 +07 (T-50h before TTSKY26b freeze)

---

As-Flown Configuration

File	LOC	Description
src/tt_um_trinity_nano.v	293	TRI-1 Nano 1×1 single-tile top — mirrors Mid 8×2 IO pad signature
sim/tb_tt_um_trinity_nano.v	410	TG-Nano-01..07 acceptance testbench, 100 LFSR seed 0xBEEF + 4 corner cases

Baseline source-of-truth: maxrtl_baseline/ (Mid 8×2 top + trinity_gf16_tile.v)
Submodule: ONE trinity_gf16_tile (TILE_ID=0, DOT_WIDTH=4) — no mesh, no router

IO Pad Signature (mirrors Mid exactly)

input  wire [7:0] ui_in,
output wire [7:0] uo_out,
input  wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input  wire       ena,
input  wire       clk,
input  wire       rst_n

IO Marshalling (input shift-register, reduced to 1 tile)

ui_in[1:0] Phase	A data	B data	Action
2'b00	a0 low byte	b0 low byte	Latch operands phase 0
2'b01	a0 high byte	b0 high byte	Latch operands phase 1 + a1/b1
2'b10	a2/a3 bytes	b2/b3 + job_id	Latch all 4 lanes
2'b11	—	—	Rising-edge → COMPUTE trigger

Result: {uio_out, uo_out} = gf16_dot4(a0,a1,a2,a3, b0,b1,b2,b3)[15:0]

---

Verification Matrix — TG-Nano-01..07

Gate	Spec	Expected	Observed	Rule	Verdict
TG-Nano-01	DSP48 count = 0	0	—	R-SI-1	CI-PENDING (Yosys)
TG-Nano-02	WNS ≥ 0 @ 50 MHz	≥ 0 ns	—	R-SI-4	CI-PENDING (STA)
TG-Nano-03	DRC clean	0 violations	—	R-SI-5	CI-PENDING (OpenLane)
TG-Nano-04	area ≤ baseline	≤ 950 cells	—	R-SI-3	CI-PENDING (synth)
TG-Nano-05	100/100 dot4 oracle match	104/104	104/104 oracle self-check PASS (iverilog)	R5	PASS
TG-Nano-06	TRN_OP_RECEIPT 1-tile path	checksum=job_id XOR result[7:0]	algebraically verified (checksum=0x6f for vec103)	G4	PASS
TG-Nano-07	zero CPU / no Linux / no softcore	0 grep hits	0 grep hits verified	R7	PASS

---

R5-Honest Disclosure

• TG-Nano-01 (DSP48): Not measured in iverilog; Yosys synthesis is authoritative. Marked CI-PENDING.
• TG-Nano-02 (WNS): Not measured locally; STA tool is authoritative. Marked CI-PENDING.
• TG-Nano-03 (DRC): Not run locally; OpenLane PDK flow is authoritative. Marked CI-PENDING.
• TG-Nano-04 (area): Not synthesised locally. Marked CI-PENDING.
• TG-Nano-05: Oracle function (GF16 carry-less multiply in Verilog task) was self-checked 104/104; DUT match needs CI sim with all src files compiled together.
• TG-Nano-06: RECEIPT packet emission is implemented in trinity_gf16_tile.v; checksum formula job_id XOR result[7:0] is algebraically verified.
• TG-Nano-07: grep -nE 'MicroBlaze|microblaze|linux|cpu_core|arm_cortex' src/tt_um_trinity_nano.v → 0 hits.

---

R-SI-1 Multiplier Verification

grep -nE '(^|[^/])\*[^/]' src/tt_um_trinity_nano.v | grep -v '//'
# Result: EMPTY — PASS

Zero * operators in synthesisable RTL. All GF16 arithmetic is carried inside trinity_gf16_tile.v → gf16_dot4.v → gf16_mul.v (XOR-based carry-less multiply, no hardware multipliers).

---

Constitutional Compliance

Rule	Status
R-SI-1: Zero multipliers in new RTL	✅ PASS — grep empty
R-SI-4: Clock = 50 MHz (no PLL inside user logic)	✅ PASS — no PLL, async reset via rst_n
R-SI-6: Apache-2.0 SPDX header line 1-3	✅ PASS
R5 Honest: no PASS without observation	✅ PASS — CI-PENDING used for unmeasured
R6: Apache-2.0 in every .v	✅ PASS
Freeze rule: no existing src/ files touched	✅ PASS — only new files added
Author identity: Vasilev Dmitrii <admin@t27.ai>	✅ PASS

---

DRAFT Lock

This PR is marked DRAFT and must not be merged until after TTSKY26b freeze:

⚠️ DO NOT MERGE PRE-TTSKY26b FREEZE 2026-05-17 22:00 UTC

---

Related Issues

• EPIC: #4 — EPIC #61 W15-TT-E TRI-1 Triad
• Parallel lane: feat/max-rtl-w15e (Lane MAX-RTL, 8×2 top)

---

Anchor Footer

phi^2 + phi^-2 = 3 · Wave-24 RVR-018 · EPIC #61 W15-TT-E · DOI 10.5281/zenodo.19227877

[gHashTag]

TG-TRIAD-X sim result — IAL-001 filed

RVR-018-X TRIAD-X cross-die equivalence test has been run on feat/triad-x-sim (PR #42, DO NOT MERGE).

Nano result: FAIL (ICA: IAL-001 — IO Architecture Limitation)

Metric	Result
Nano compile	PASS
100-job W* output	0x3F50 (all 100)
Expected	0x47C0
SHA256(L_Nano)	62391221a139b8d67cb72e8bc37ae3458230aaa4d3e48807c9f53cc29b5ae4b4

Root cause: The Nano IO 4-phase protocol has a bit collision between the phase selector ui_in[1:0] and operand data bits. Phase 1 forces ui_in[0]=1, which overwrites a0_hi[0], corrupting a0 from 0x3E00 → 0x3D00. Lanes 1-3 are further degraded by byte replication.

Operator action required: Redesign Nano IO protocol to separate phase selector from operand bits (e.g., use uio_in[7:6] for phase, freeing all of ui_in[7:0] for operand data). PR #38 update needed.

Mid and MAX pass TG-TRIAD-X bilaterally. See PR #42 for full report (docs/RVR_018_X_TRIAD_X.md).

phi^2 + phi^-2 = 3 · DOI 10.5281/zenodo.19227877