[T-0 SIM EVIDENCE DRAFT] feat(sim): RVR-018-X TG-TRIAD-X cross-die SHA256 equivalence · DO NOT MERGE · integration-branch artefact#42
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May 15, 2026 08:43
…RGE PRE-TTSKY26b
- src/trinity_router_4x4.v: 16-node XY router (extends trinity_router_2x2 pattern)
192 LOC; 4-bit flat node_id={y[1:0],x[1:0]}; 16-way RR arbitration
- src/trinity_mesh_4x4.v: 16 trinity_gf16_tile via generate-for (extends 2x2)
118 LOC; ICA-002: DST rewrite for 2-bit TILE_ID compat; DOT_WIDTH=4
- src/tt_um_trinity_max.v: TT MAX top wrapper (mirrors tt_um_ghtag_trinity_gf16)
164 LOC; same IO pad set; instantiates trinity_mesh_4x4; area ~4x Mid
- sim/tb_trinity_mesh_4x4.v: TG-Max-01..07 acceptance gate testbench
329 LOC; LFSR seed 0xBEEF; 100 LFSR vectors + canonical 0x47C0 check
- R-SI-1: grep verified 0 * in synthesisable RTL (arithmetic multiply)
- R5 HONEST: STA/DRC/area marked CI-PENDING (no local Yosys/OpenLane2)
- TG-Max-07: grep confirmed zero MicroBlaze/CPU/Linux in compute core
- Anchor: phi^2 + phi^-2 = 3 · Wave-24 RVR-018 · EPIC #61 W15-TT-E · DOI 10.5281/zenodo.19227877
Vasilev Dmitrii <admin@t27.ai>
- Add sim/tb_tg_triad_x.v: 3-DUT TRIAD-X testbench (Mid + MAX + Nano side-by-side) - Add docs/RVR_018_X_TRIAD_X.md: NASA-style simulation report - Cherry-pick src/tt_um_trinity_nano.v from feat/nano-rtl-w15e Sim result: Mid+MAX PASS 100/100 (0x47C0), Nano FAIL 100/100 (0x3F50) Root cause: Nano IO phase encoding collision prevents W* operand injection SHA256(L_Mid) == SHA256(L_Max): ef346f3291c8cfb47f13cec15736c698690058cba1cab7cbff65bfac3330ab00 SHA256(L_Nano): 62391221a139b8d67cb72e8bc37ae3458230aaa4d3e48807c9f53cc29b5ae4b4 ICA filed: IAL-001 (Nano IO Architecture Limitation) EPIC #49 S2 + EPIC #61 Anchor: phi^2 + phi^-2 = 3 · DOI 10.5281/zenodo.19227877
This was referenced May 15, 2026
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[T-0 SIM EVIDENCE DRAFT] TG-TRIAD-X Cross-Die SHA256 Equivalence
DO NOT MERGE — This is a simulation evidence artifact on an integration branch.
Summary
This PR provides simulation proof for TG-TRIAD-X (cross-die R7 Popper gate) from EPIC #49 §2 + EPIC #61.
Files Added
sim/tb_tg_triad_x.v: 357-line TRIAD-X testbench instantiating all 3 TRI-1 SKUs side-by-sidedocs/RVR_018_X_TRIAD_X.md: NASA-style simulation report (RVR-018-X-TRIAD-X)src/tt_um_trinity_nano.v: cherry-picked from feat/nano-rtl-w15e (PR [WAVE-24 W15-TT-E] feat(silicon): TRI-1 Nano 1x1 single-tile top · EPIC #61 · DO NOT MERGE PRE-TTSKY26b #38) for integrationSimulation Results
ef346f3291c8cfb47f13cec15736c698690058cba1cab7cbff65bfac3330ab00ef346f3291c8cfb47f13cec15736c698690058cba1cab7cbff65bfac3330ab0062391221a139b8d67cb72e8bc37ae3458230aaa4d3e48807c9f53cc29b5ae4b4TG-TRIAD-X Verdict
FAIL — Nano diverges at all 100 jobs.
SHA256(L_Mid) == SHA256(L_Max): ✓ PASS
SHA256(L_Mid) == SHA256(L_Nano): ✗ FAIL
Root Cause: IAL-001 (Nano IO Architecture Limitation)
The Nano's 4-phase IO protocol overlaps the phase selector bits with operand data bits.
When driving W*=(1,2,3,4) operands,
ui_in[1:0](phase) overwritesa0_byte[1:0], corruptinga0_hifrom 0x3E → 0x3D (bit 0 collision). Lanes 1-3 are further degraded by replication.Actual operands loaded: a0=0x3D00, a1=0x3D3D, a2=0x0202, a3=0x0021
dot4(actual) ≈ 1.66 = 0x3F50 (vs expected 30.0 = 0x47C0)
ICA filed: IAL-001
Operator action required: Decide whether to redesign Nano IO protocol (PR #38 update) or redefine W*_Nano.
Branch Structure (R5 Honest Disclosure)
This TB lives on
feat/triad-x-sim(temporary integration branch).Base:
feat/max-rtl-w15e(PR #39) +tt_um_trinity_nano.vcherry-picked fromfeat/nano-rtl-w15e(PR #38).Merging to main requires both PR #38 + PR #39 to land first.
Relates to: #38 #39 #49 #61
Anchor:
phi^2 + phi^-2 = 3 · DOI 10.5281/zenodo.19227877